Blink: Fast Automated Design of Run-Time Power Monitors on FPGA-Based Computing Platforms
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arXiv
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| Main Authors: | , , |
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| Format: | Preprint |
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2024
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| _version_ | 1866910804023967744 |
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| author | Galimberti, Andrea Piccoli, Michele Zoni, Davide |
| author_facet | Galimberti, Andrea Piccoli, Michele Zoni, Davide |
| contents | The current over-provisioned heterogeneous multi-cores require effective run-time optimization strategies, and the run-time power monitoring subsystem is paramount for their success. Several state-of-the-art methodologies address the design of a run-time power monitoring infrastructure for generic computing platforms. However, the power model's training requires time-consuming gate-level simulations that, coupled with the ever-increasing complexity of the modern heterogeneous platforms, dramatically hinder the usability of such solutions. This paper introduces Blink, a scalable framework for the fast and automated design of run-time power monitoring infrastructures targeting computing platforms implemented on FPGA. Blink optimizes the time-to-solution to deliver the run-time power monitoring infrastructure by replacing traditional methodologies' gate-level simulations and power trace computations with behavioral simulations and direct power trace measurements. Applying Blink to multiple designs mixing a set of HLS-generated accelerators from a state-of-the-art benchmark suite demonstrates an average time-to-solution speedup of 18 times without affecting the quality of the run-time power estimates. |
| format | Preprint |
| id |
arxiv_https___arxiv_org_abs_2407_21367 |
| institution | arXiv |
| publishDate | 2024 |
| record_format | arxiv |
| spellingShingle | Blink: Fast Automated Design of Run-Time Power Monitors on FPGA-Based Computing Platforms Galimberti, Andrea Piccoli, Michele Zoni, Davide Hardware Architecture The current over-provisioned heterogeneous multi-cores require effective run-time optimization strategies, and the run-time power monitoring subsystem is paramount for their success. Several state-of-the-art methodologies address the design of a run-time power monitoring infrastructure for generic computing platforms. However, the power model's training requires time-consuming gate-level simulations that, coupled with the ever-increasing complexity of the modern heterogeneous platforms, dramatically hinder the usability of such solutions. This paper introduces Blink, a scalable framework for the fast and automated design of run-time power monitoring infrastructures targeting computing platforms implemented on FPGA. Blink optimizes the time-to-solution to deliver the run-time power monitoring infrastructure by replacing traditional methodologies' gate-level simulations and power trace computations with behavioral simulations and direct power trace measurements. Applying Blink to multiple designs mixing a set of HLS-generated accelerators from a state-of-the-art benchmark suite demonstrates an average time-to-solution speedup of 18 times without affecting the quality of the run-time power estimates. |
| title | Blink: Fast Automated Design of Run-Time Power Monitors on FPGA-Based Computing Platforms |
| topic | Hardware Architecture |
| url | https://arxiv.org/abs/2407.21367 |