Towards Error Correction for Computing in Racetrack Memory
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arXiv
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| Auteurs principaux: | , , , , , , |
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| Format: | Preprint |
| Publié: |
2024
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| _version_ | 1866917738152198144 |
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| author | Brazzle, Preston Morris III, Benjamin F. McKinney, Evan Zhou, Peipei Hu, Jingtong Khan, Asif Ali Jones, Alex K. |
| author_facet | Brazzle, Preston Morris III, Benjamin F. McKinney, Evan Zhou, Peipei Hu, Jingtong Khan, Asif Ali Jones, Alex K. |
| contents | Computing-in-memory (CIM) promises to alleviate the Von Neumann bottleneck and accelerate data-intensive applications. Depending on the underlying technology and configuration, CIM enables implementing compute primitives in place, such as multiplication, search operations, and bulk bitwise logic operations. Emerging nonvolatile memory technologies such as spintronic Racetrack memory (RTM) promise not only unprecedented density but also significant parallelism through CIM. However, most CIM designs, including those based on RTM, exhibit high fault rates. Existing error correction codes (ECC) are not homomorphic over bitwise operations such as AND and OR, and hence cannot protect against CIM faults. This paper proposes CIRM-ECC, a technique to protect spintronic RTMs against CIM faults. At the core of CIRM-ECC, we use a recently proposed RTM-based CIM approach and leverage its peripheral circuitry to our implement our novel ECC codes. We show that CIRM-ECC can be applied to single-bit Hamming codes as well as multi-bit BCH codes. |
| format | Preprint |
| id |
arxiv_https___arxiv_org_abs_2407_21661 |
| institution | arXiv |
| publishDate | 2024 |
| record_format | arxiv |
| spellingShingle | Towards Error Correction for Computing in Racetrack Memory Brazzle, Preston Morris III, Benjamin F. McKinney, Evan Zhou, Peipei Hu, Jingtong Khan, Asif Ali Jones, Alex K. Hardware Architecture Computing-in-memory (CIM) promises to alleviate the Von Neumann bottleneck and accelerate data-intensive applications. Depending on the underlying technology and configuration, CIM enables implementing compute primitives in place, such as multiplication, search operations, and bulk bitwise logic operations. Emerging nonvolatile memory technologies such as spintronic Racetrack memory (RTM) promise not only unprecedented density but also significant parallelism through CIM. However, most CIM designs, including those based on RTM, exhibit high fault rates. Existing error correction codes (ECC) are not homomorphic over bitwise operations such as AND and OR, and hence cannot protect against CIM faults. This paper proposes CIRM-ECC, a technique to protect spintronic RTMs against CIM faults. At the core of CIRM-ECC, we use a recently proposed RTM-based CIM approach and leverage its peripheral circuitry to our implement our novel ECC codes. We show that CIRM-ECC can be applied to single-bit Hamming codes as well as multi-bit BCH codes. |
| title | Towards Error Correction for Computing in Racetrack Memory |
| topic | Hardware Architecture |
| url | https://arxiv.org/abs/2407.21661 |