Imagen de Portada

ChipExpert: The Open-Source Integrated-Circuit-Design-Specific Large Language Model

Fuente: arXiv

Guardado en:

Detalles Bibliográficos
Autores principales:	Xu, Ning, Zhang, Zhaoyang, Qi, Lei, Wang, Wensuo, Zhang, Chao, Ren, Zihao, Zhang, Huaiyuan, Cheng, Xin, Zhang, Yanqi, Liu, Zhichao, Wei, Qingwen, Wu, Shiyang, Yang, Lanlan, Lu, Qianfeng, Ma, Yiqun, Zhao, Mengyao, Liu, Junbo, Song, Yufan, Geng, Xin, Yang, Jun
Formato:	Preprint
Publicado:	2024
Materias:	Hardware Architecture Artificial Intelligence Machine Learning
Acceso en línea:	Acceder al recurso
Etiquetas:	Agregar Etiqueta Sin Etiquetas, Sea el primero en etiquetar este registro!

Ejemplares similares

ChipMind: Retrieval-Augmented Reasoning for Long-Context Circuit Design Specifications
por: Xing, Changwen, et al.
Publicado: (2025)

Mozart: A Chiplet Ecosystem-Accelerator Codesign Framework for Composable Bespoke Application Specific Integrated Circuits
por: Jin, Haoran, et al.
Publicado: (2025)

CircuitFusion: Multimodal Circuit Representation Learning for Agile Chip Design
por: Fang, Wenji, et al.
Publicado: (2025)

Large Processor Chip Model
por: Chang, Kaiyan, et al.
Publicado: (2025)

Ultra Low-Power SDM-based Circuit-Switching for Networks-on-Chip
por: Zaeemi, Meysam, et al.
Publicado: (2026)

TaiBai: A fully programmable brain-inspired processor with topology-aware efficiency
por: Li, Qianpeng, et al.
Publicado: (2025)

AutoPDR: Circuit-Aware Solver Configuration Prediction for Hardware Model Checking
por: Hu, Guangyu, et al.
Publicado: (2026)

Sieve: Dynamic Expert-Aware PIM Acceleration for Evolving Mixture-of-Experts Models
por: Kim, Jungwoo, et al.
Publicado: (2026)

RRAM-Based Bio-Inspired Circuits for Mobile Epileptic Correlation Extraction and Seizure Prediction
por: Wang, Hao, et al.
Publicado: (2024)

What Is Next for LLMs? Next-Generation AI Computing Hardware Using Photonic Chips
por: Li, Renjie, et al.
Publicado: (2025)

AnalogGenie: A Generative Engine for Automatic Discovery of Analog Circuit Topologies
por: Gao, Jian, et al.
Publicado: (2025)

ZeroSim: Zero-Shot Analog Circuit Evaluation with Unified Transformer Embeddings
por: Yang, Xiaomeng, et al.
Publicado: (2025)

Optimizing and Exploring System Performance in Compact Processing-in-Memory-based Chips
por: Chen, Peilin, et al.
Publicado: (2025)

Breaking the HBM Bit Cost Barrier: Domain-Specific ECC for AI Inference Infrastructure
por: Xie, Rui, et al.
Publicado: (2025)

Benchmarking End-To-End Performance of AI-Based Chip Placement Algorithms
por: Wang, Zhihai, et al.
Publicado: (2024)

TEMP: A Memory Efficient Physical-aware Tensor Partition-Mapping Framework on Wafer-scale Chips
por: Wang, Huizheng, et al.
Publicado: (2025)

Graphitron: A Domain Specific Language for FPGA-based Graph Processing Accelerator Generation
por: Zhang, Xinmiao, et al.
Publicado: (2024)

A Review of SRAM-based Compute-in-Memory Circuits
por: Yoshioka, Kentaro, et al.
Publicado: (2024)

LaMAGIC: Language-Model-based Topology Generation for Analog Integrated Circuits
por: Chang, Chen-Chia, et al.
Publicado: (2024)

AssertLLM: Generating Hardware Verification Assertions from Design Specifications via Multi-LLMs
por: Yan, Zhiyuan, et al.
Publicado: (2024)

Retrieve, Schedule, Reflect: LLM Agents for Chip QoR Optimization
por: ouyang, Yikang, et al.
Publicado: (2026)

On-Chip Hardware-Aware Quantization for Mixed Precision Neural Networks
por: Huang, Wei, et al.
Publicado: (2023)

AssertLLM: Generating and Evaluating Hardware Verification Assertions from Design Specifications via Multi-LLMs
por: Fang, Wenji, et al.
Publicado: (2024)

Expert Streaming: Accelerating Low-Batch MoE Inference via Multi-chiplet Architecture and Dynamic Expert Trajectory Scheduling
por: Ma, Songchen, et al.
Publicado: (2026)

HFRWKV: A High-Performance Fully On-Chip Hardware Accelerator for RWKV
por: Shijie, Liu, et al.
Publicado: (2026)

ASiM: Modeling and Analyzing Inference Accuracy of SRAM-Based Analog CiM Circuits
por: Zhang, Wenlun, et al.
Publicado: (2024)

LaMAGIC2: Advanced Circuit Formulations for Language Model-Based Analog Topology Generation
por: Chang, Chen-Chia, et al.
Publicado: (2025)

IICPilot: An Intelligent Integrated Circuit Backend Design Framework Using Open EDA
por: Jiang, Zesong, et al.
Publicado: (2024)

ChipBench: A Next-Step Benchmark for Evaluating LLM Performance in AI-Aided Chip Design
por: Yu, Zhongkai, et al.
Publicado: (2026)

SpecLLM: Exploring Generation and Review of VLSI Design Specification with Large Language Model
por: Li, Mengming, et al.
Publicado: (2024)

Area-Efficient In-Memory Computing for Mixture-of-Experts via Multiplexing and Caching
por: Gao, Hanyuan, et al.
Publicado: (2026)

Circuit Diagram Retrieval Based on Hierarchical Circuit Graph Representation
por: Gao, Ming, et al.
Publicado: (2025)

Scope: A Scalable Merged Pipeline Framework for Multi-Chip-Module NN Accelerators
por: Huang, Zongle, et al.
Publicado: (2026)

Versatile silicon integrated photonic processor: a reconfigurable solution for next-generation AI clusters
por: Zhu, Ying, et al.
Publicado: (2025)

AC-Refiner: Efficient Arithmetic Circuit Optimization Using Conditional Diffusion Models
por: Xue, Chenhao, et al.
Publicado: (2025)

FLAG: Formal and LLM-assisted SVA Generation for Formal Specifications of On-Chip Communication Protocols
por: Shih, Yu-An, et al.
Publicado: (2025)

Rome was Not Built in a Single Step: Hierarchical Prompting for LLM-based Chip Design
por: Nakkab, Andre, et al.
Publicado: (2024)

RoSE-Opt: Robust and Efficient Analog Circuit Parameter Optimization with Knowledge-infused Reinforcement Learning
por: Cao, Weidong, et al.
Publicado: (2024)

Theseus: Exploring Efficient Wafer-Scale Chip Design for Large Language Models
por: Zhu, Jingchen, et al.
Publicado: (2024)

RISC-Q: A Generator for Real-Time Quantum Control System-on-Chips Compatible with RISC-V
por: Liu, Junyi, et al.
Publicado: (2025)