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| Main Authors: | , , , |
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| Format: | Preprint |
| Published: |
2024
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| Subjects: | |
| Online Access: | https://arxiv.org/abs/2408.00806 |
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| _version_ | 1866917888664797184 |
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| author | Kokane, Omkar Sati, Prabhat Lokhande, Mukul Vishvakarma, Santosh Kumar |
| author_facet | Kokane, Omkar Sati, Prabhat Lokhande, Mukul Vishvakarma, Santosh Kumar |
| contents | This paper presents the Hybrid Overestimating Approximate Adder designed to enhance the performance in processing engines, specifically focused on edge AI applications. A novel Plus One Adder design is proposed as an incremental adder in the RCA chain, incorporating a Full Adder with an excess 1 alongside inputs A, B, and Cin. The design approximates outputs to 2 bit values to reduce hardware complexity and improve resource efficiency. The Plus One Adder is integrated into a dynamically reconfigurable HOAA, allowing runtime interchangeability between accurate and approximate overestimation modes. The proposed design is demonstrated for multiple applications, such as Twos complement subtraction and Rounding to even, and the Configurable Activation function, which are critical components of the Processing engine. Our approach shows 21 percent improvement in area efficiency and 33 percent reduction in power consumption, compared to state of the art designs with minimal accuracy loss. Thus, the proposed HOAA could be a promising solution for resource-constrained environments, offering ideal trade-offs between hardware efficiency vs computational accuracy. |
| format | Preprint |
| id |
arxiv_https___arxiv_org_abs_2408_00806 |
| institution | arXiv |
| publishDate | 2024 |
| record_format | arxiv |
| spellingShingle | HOAA: Hybrid Overestimating Approximate Adder for Enhanced Performance Processing Engine Kokane, Omkar Sati, Prabhat Lokhande, Mukul Vishvakarma, Santosh Kumar Hardware Architecture Artificial Intelligence Computer Vision and Pattern Recognition This paper presents the Hybrid Overestimating Approximate Adder designed to enhance the performance in processing engines, specifically focused on edge AI applications. A novel Plus One Adder design is proposed as an incremental adder in the RCA chain, incorporating a Full Adder with an excess 1 alongside inputs A, B, and Cin. The design approximates outputs to 2 bit values to reduce hardware complexity and improve resource efficiency. The Plus One Adder is integrated into a dynamically reconfigurable HOAA, allowing runtime interchangeability between accurate and approximate overestimation modes. The proposed design is demonstrated for multiple applications, such as Twos complement subtraction and Rounding to even, and the Configurable Activation function, which are critical components of the Processing engine. Our approach shows 21 percent improvement in area efficiency and 33 percent reduction in power consumption, compared to state of the art designs with minimal accuracy loss. Thus, the proposed HOAA could be a promising solution for resource-constrained environments, offering ideal trade-offs between hardware efficiency vs computational accuracy. |
| title | HOAA: Hybrid Overestimating Approximate Adder for Enhanced Performance Processing Engine |
| topic | Hardware Architecture Artificial Intelligence Computer Vision and Pattern Recognition |
| url | https://arxiv.org/abs/2408.00806 |