Cover Image

TrIM, Triangular Input Movement Systolic Array for Convolutional Neural Networks: Dataflow and Analytical Modelling

Fuente: arXiv

Saved in:

Bibliographic Details
Main Authors:	Sestito, Cristian, Agwa, Shady, Prodromakis, Themis
Format:	Preprint
Published:	2024
Subjects:	Artificial Intelligence Hardware Architecture
Online Access:	Acceder al recurso
Tags:	Add Tag No Tags, Be the first to tag this record!

Similar Items

TrIM, Triangular Input Movement Systolic Array for Convolutional Neural Networks: Architecture and Hardware Implementation
by: Sestito, Cristian, et al.
Published: (2024)

3D-TrIM: A Memory-Efficient Spatial Computing Architecture for Convolution Workloads
by: Sestito, Cristian, et al.
Published: (2025)

DiP: A Scalable, Energy-Efficient Systolic Array for Matrix Multiplication Acceleration
by: Abdelmaksoud, Ahmed J., et al.
Published: (2024)

ADiP: Adaptive-Precision Systolic Array for Matrix Multiplication Acceleration
by: Abdelmaksoud, Ahmed J., et al.
Published: (2025)

OISMA: On-the-fly In-memory Stochastic Multiplication Architecture for Matrix-Multiplication Workloads
by: Agwa, Shady, et al.
Published: (2025)

DISCA: A Digital In-memory Stochastic Computing Architecture Using A Compressed Bent-Pyramid Format
by: Agwa, Shady, et al.
Published: (2025)

A Hybrid Edge Classifier: Combining TinyML-Optimised CNN with RRAM-CMOS ACAM for Energy-Efficient Inference
by: Woodward, Kieran, et al.
Published: (2025)

A 9T4R RRAM-Based ACAM for Analogue Template Matching at the Edge
by: Papandroulidakis, Georgios, et al.
Published: (2024)

Hybrid Systolic Array Accelerator with Optimized Dataflow for Edge Large Language Model Inference
by: Chen, Chun-Ting, et al.
Published: (2025)

D-Legion: A Scalable Many-Core Architecture for Accelerating Matrix Multiplication in Quantized LLMs
by: Abdelmaksoud, Ahmed J., et al.
Published: (2026)

SystolicAttention: Fusing FlashAttention within a Single Systolic Array
by: Lin, Jiawei, et al.
Published: (2025)

KAN-SAs: Efficient Acceleration of Kolmogorov-Arnold Networks on Systolic Arrays
by: Errabii, Sohaib, et al.
Published: (2025)

Bitwise Systolic Array Architecture for Runtime-Reconfigurable Multi-precision Quantized Multiplication on Hardware Accelerators
by: Liu, Yuhao, et al.
Published: (2026)

SA-Kura: An Energy-Efficient Systolic Array Accelerator for Locally-Coupled Kuramoto Drift in Diffusion Sampling
by: Jin, Jeongmin, et al.
Published: (2026)

Computing-In-Memory Dataflow for Minimal Buffer Traffic
by: Song, Choongseok, et al.
Published: (2025)

SAFFIRA: a Framework for Assessing the Reliability of Systolic-Array-Based DNN Accelerators
by: Taheri, Mahdi, et al.
Published: (2024)

ReDas: A Lightweight Architecture for Supporting Fine-Grained Reshaping and Multiple Dataflows on Systolic Array
by: Han, Meng, et al.
Published: (2023)

VUSA: Virtually Upscaled Systolic Array Architecture to Exploit Unstructured Sparsity in AI Acceleration
by: Helal, Shereef, et al.
Published: (2025)

Explainable AI-Guided Efficient Approximate DNN Generation for Multi-Pod Systolic Arrays
by: Siddique, Ayesha, et al.
Published: (2025)

LoAS: Fully Temporal-Parallel Dataflow for Dual-Sparse Spiking Neural Networks
by: Yin, Ruokai, et al.
Published: (2024)

Systolic Array Data Flows for Efficient Matrix Multiplication in Deep Neural Networks
by: Raja, Tejas
Published: (2024)

FlexiSAGA: A Flexible Systolic Array GEMM Accelerator for Sparse and Dense Processing
by: Müller, Mika Markus, et al.
Published: (2025)

On-Sensor Convolutional Neural Networks with Early-Exits
by: Shalby, Hazem Hesham Yousef, et al.
Published: (2025)

Seizure Detection and Prediction by Parallel Memristive Convolutional Neural Networks
by: Li, Chenqi, et al.
Published: (2022)

SISA: A Scale-In Systolic Array for GEMM Acceleration
by: Altamura, Luigi, et al.
Published: (2026)

Error Checking for Sparse Systolic Tensor Arrays
by: Peltekis, Christodoulos, et al.
Published: (2024)

Dataflow-Aware PIM-Enabled Manycore Architecture for Deep Learning Workloads
by: Sharma, Harsh, et al.
Published: (2024)

Low-Rank Compression for IMC Arrays
by: Jeon, Kang Eun, et al.
Published: (2025)

RAGnaroX: A Secure, Local-Hosted ChatOps Assistant Using Small Language Models
by: Dornauer, Benedikt, et al.
Published: (2026)

BF-IMNA: A Bit Fluid In-Memory Neural Architecture for Neural Network Acceleration
by: Rakka, Mariam, et al.
Published: (2024)

MEADOW: Memory-efficient Dataflow and Data Packing for Low Power Edge LLMs
by: Moitra, Abhishek, et al.
Published: (2025)

Benchmarking Deep Learning Convolutions on Energy-constrained CPUs
by: Galvez, Enrique, et al.
Published: (2025)

LLMulator: Generalizable Cost Modeling for Dataflow Accelerators with Input-Adaptive Control Flow
by: Chang, Kaiyan, et al.
Published: (2025)

BiKA: Kolmogorov-Arnold-Network-inspired Ultra Lightweight Neural Network Hardware Accelerator
by: Liu, Yuhao, et al.
Published: (2026)

Monitor Placement for Fault Localization in Deep Neural Network Accelerators
by: Liu, Wei-Kai
Published: (2023)

Low Power Approximate Multiplier Architecture for Deep Neural Networks
by: Jaswal, Pragun, et al.
Published: (2025)

Natural Language to Verilog: Design of a Recurrent Spiking Neural Network using Large Language Models and ChatGPT
by: Vitolo, Paola, et al.
Published: (2024)

A Configurable and Efficient Memory Hierarchy for Neural Network Hardware Accelerator
by: Bause, Oliver, et al.
Published: (2024)

Accelerating MRI Uncertainty Estimation with Mask-based Bayesian Neural Network
by: Zhang, Zehuan, et al.
Published: (2024)

Comprehensive Design Space Exploration for Tensorized Neural Network Hardware Accelerators
by: Zhang, Jinsong, et al.
Published: (2025)