Evaluating Large Language Models for Automatic Register Transfer Logic Generation via High-Level Synthesis

Fuente: arXiv

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Bibliographic Details
Main Authors:	Swaroopa, Sneha, Mukherjee, Rijoy, Debnath, Anushka, Chakraborty, Rajat Subhra
Format:	Preprint
Published:	2024
Subjects:	Hardware Architecture
Online Access:	Acceder al recurso
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Internet

https://arxiv.org/abs/2408.02793