Cover Image

Evaluating Large Language Models for Automatic Register Transfer Logic Generation via High-Level Synthesis

Fuente: arXiv

Saved in:

Bibliographic Details
Main Authors:	Swaroopa, Sneha, Mukherjee, Rijoy, Debnath, Anushka, Chakraborty, Rajat Subhra
Format:	Preprint
Published:	2024
Subjects:	Hardware Architecture
Online Access:	Acceder al recurso
Tags:	Add Tag No Tags, Be the first to tag this record!

Similar Items

PUFBind: PUF-Enabled Lightweight Program Binary Authentication for FPGA-based Embedded Systems
by: Swaroopa, Sneha, et al.
Published: (2025)

Automatic Hardware Pragma Insertion in High-Level Synthesis: A Non-Linear Programming Approach
by: Pouget, Stéphane, et al.
Published: (2024)

Optimizing High-Level Synthesis Designs with Retrieval-Augmented Large Language Models
by: Xu, Haocheng, et al.
Published: (2024)

Relational Hoare Logic for High-Level Synthesis of Hardware Accelerators
by: Tanaka, Izumi, et al.
Published: (2026)

RTLFixer: Automatically Fixing RTL Syntax Errors with Large Language Models
by: Tsai, Yun-Da, et al.
Published: (2023)

Spec2Assertion: Automatic Pre-RTL Assertion Generation using Large Language Models with Progressive Regularization
by: Wu, Fenghua, et al.
Published: (2025)

HLSPilot: LLM-based High-Level Synthesis
by: Xiong, Chenwei, et al.
Published: (2024)

Dynamic Loop Fusion in High-Level Synthesis
by: Szafarczyk, Robert, et al.
Published: (2025)

ATLAAS: Automatic Tensor-Level Abstraction of Accelerator Semantics
by: Gao, Ruijie, et al.
Published: (2026)

System-Level Design Space Exploration for High-Level Synthesis under End-to-End Latency Constraints
by: Liao, Yuchao, et al.
Published: (2024)

DAE4HLS: Exposing Memory-Level Parallelism for High-Level Synthesis using Explicit Decoupling
by: Metz, David, et al.
Published: (2026)

Register Dispersion: Reducing the Footprint of the Vector Register File in Vector Engines of Low-Cost RISC-V CPUs
by: Titopoulos, Vasileios, et al.
Published: (2025)

Conditional Flood Fill Method in Logic Synthesis
by: Yang, Shitian, et al.
Published: (2023)

SimulatorCoder: DNN Accelerator Simulator Code Generation and Optimization via Large Language Models
by: Xia, Yuhuan, et al.
Published: (2026)

Intelligent4DSE: Optimizing High-Level Synthesis Design Space Exploration with Graph Neural Networks and Large Language Models
by: Xu, Lei, et al.
Published: (2025)

ChatHLS: Towards Systematic Design Automation and Optimization for High-Level Synthesis
by: Li, Runkai, et al.
Published: (2025)

High-Level Synthesis of Digital Circuits from Template Haskell and SDF-AP
by: Folmer, Hendrik, et al.
Published: (2025)

FIFOAdvisor: A DSE Framework for Automated FIFO Sizing of High-Level Synthesis Designs
by: Abi-Karam, Stefan, et al.
Published: (2025)

High-Level Synthesis using SDF-AP, Template Haskell, QuasiQuotes, and GADTs to Generate Circuits from Hierarchical Input Specification
by: Folmer, Hendrik
Published: (2025)

Switchable Single/Dual Edge Registers for Pipeline Architecture
by: Singh, Suyash Vardhan, et al.
Published: (2024)

RealProbe: An Automated and Lightweight Performance Profiler for In-FPGA Execution of High-Level Synthesis Designs
by: Kim, Jiho, et al.
Published: (2025)

Synthesis of Resource-Efficient Superconducting Circuits with Clock-Free Alternating Logic
by: Volk, Jennifer, et al.
Published: (2024)

E-morphic: Scalable Equality Saturation for Structural Exploration in Logic Synthesis
by: Chen, Chen, et al.
Published: (2025)

Leveraging High-Level Synthesis and Large Language Models to Generate, Simulate, and Deploy a Uniform Random Number Generator Hardware Design
by: Meech, James T.
Published: (2023)

R-HLS: An IR for Dynamic High-Level Synthesis and Memory Disambiguation based on Regions and State Edges
by: Metz, David, et al.
Published: (2024)

LPU: A Latency-Optimized and Highly Scalable Processor for Large Language Model Inference
by: Moon, Seungjae, et al.
Published: (2024)

Chiplet Cloud: Building AI Supercomputers for Serving Large Generative Language Models
by: Peng, Huwan, et al.
Published: (2023)

AssertFix: Empowering Automated Assertion Fix via Large Language Models
by: Lyu, Hongqin, et al.
Published: (2025)

AnalogTester: A Large Language Model-Based Framework for Automatic Testbench Generation in Analog Circuit Design
by: Chen, Weiyu, et al.
Published: (2025)

ForgeHLS: A Large-Scale, Open-Source Dataset for High-Level Synthesis
by: Peng, Zedong, et al.
Published: (2025)

High-Level Surface Code Decoding via Parallel FFNNs on CIM Platforms
by: Wang, Hao, et al.
Published: (2024)

Improving Instruction Fetch Efficiency via High-Level Program Map Traversal
by: Murthy, Shyam, et al.
Published: (2024)

LightningSimV2: Faster and Scalable Simulation for High-Level Synthesis via Graph Compilation and Optimization
by: Sarkar, Rishov, et al.
Published: (2024)

SpecLLM: Exploring Generation and Review of VLSI Design Specification with Large Language Model
by: Li, Mengming, et al.
Published: (2024)

Timing-driven Approximate Logic Synthesis Based on Double-chase Grey Wolf Optimizer
by: Hu, Xiangfei, et al.
Published: (2024)

EdgeLLM: A Highly Efficient CPU-FPGA Heterogeneous Edge Accelerator for Large Language Models
by: Huang, Mingqiang, et al.
Published: (2024)

HLS-Eval: A Benchmark and Framework for Evaluating LLMs on High-Level Synthesis Design Tasks
by: Abi-Karam, Stefan, et al.
Published: (2025)

SA-DS: A Dataset for Large Language Model-Driven AI Accelerator Design Generation
by: Vungarala, Deepak, et al.
Published: (2024)

Are LLMs Any Good for High-Level Synthesis?
by: Liao, Yuchao, et al.
Published: (2024)

Deep Inverse Design for High-Level Synthesis
by: Chang, Ping, et al.
Published: (2024)