LLM-Aided Compilation for Tensor Accelerators
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arXiv
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| Main Authors: | , , , , , , |
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| Format: | Preprint |
| Published: |
2024
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| _version_ | 1866916349531389952 |
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| author | Hong, Charles Bhatia, Sahil Haan, Altan Dong, Shengjun Kris Nikiforov, Dima Cheung, Alvin Shao, Yakun Sophia |
| author_facet | Hong, Charles Bhatia, Sahil Haan, Altan Dong, Shengjun Kris Nikiforov, Dima Cheung, Alvin Shao, Yakun Sophia |
| contents | Hardware accelerators, in particular accelerators for tensor processing, have many potential application domains. However, they currently lack the software infrastructure to support the majority of domains outside of deep learning. Furthermore, a compiler that can easily be updated to reflect changes at both application and hardware levels would enable more agile development and design space exploration of accelerators, allowing hardware designers to realize closer-to-optimal performance. In this work, we discuss how large language models (LLMs) could be leveraged to build such a compiler. Specifically, we demonstrate the ability of GPT-4 to achieve high pass rates in translating code to the Gemmini accelerator, and prototype a technique for decomposing translation into smaller, more LLM-friendly steps. Additionally, we propose a 2-phase workflow for utilizing LLMs to generate hardware-optimized code. |
| format | Preprint |
| id |
arxiv_https___arxiv_org_abs_2408_03408 |
| institution | arXiv |
| publishDate | 2024 |
| record_format | arxiv |
| spellingShingle | LLM-Aided Compilation for Tensor Accelerators Hong, Charles Bhatia, Sahil Haan, Altan Dong, Shengjun Kris Nikiforov, Dima Cheung, Alvin Shao, Yakun Sophia Hardware Architecture Machine Learning Programming Languages Hardware accelerators, in particular accelerators for tensor processing, have many potential application domains. However, they currently lack the software infrastructure to support the majority of domains outside of deep learning. Furthermore, a compiler that can easily be updated to reflect changes at both application and hardware levels would enable more agile development and design space exploration of accelerators, allowing hardware designers to realize closer-to-optimal performance. In this work, we discuss how large language models (LLMs) could be leveraged to build such a compiler. Specifically, we demonstrate the ability of GPT-4 to achieve high pass rates in translating code to the Gemmini accelerator, and prototype a technique for decomposing translation into smaller, more LLM-friendly steps. Additionally, we propose a 2-phase workflow for utilizing LLMs to generate hardware-optimized code. |
| title | LLM-Aided Compilation for Tensor Accelerators |
| topic | Hardware Architecture Machine Learning Programming Languages |
| url | https://arxiv.org/abs/2408.03408 |