Image de couverture de livre

Exploiting the Lock: Leveraging MiG-V's Logic Locking for Secret-Data Extraction

Fuente: arXiv

Enregistré dans:

Détails bibliographiques
Auteurs principaux:	Reimann, Lennart M., Variyar, Yadu Madhukumar, Huelser, Lennet, Ghinami, Chiara, Germek, Dominik, Leupers, Rainer
Format:	Preprint
Publié:	2024
Sujets:	Cryptography and Security Hardware Architecture
Accès en ligne:	Acceder al recurso
Tags:	Ajouter un tag Pas de tags, Soyez le premier à ajouter un tag!

Documents similaires

The Impact of Logic Locking on Confidentiality: An Automated Evaluation
par: Reimann, Lennart M., et autres
Publié: (2025)

QTFlow: Quantitative Timing-Sensitive Information Flow for Security-Aware Hardware Design on RTL
par: Reimann, Lennart M., et autres
Publié: (2024)

Automatic Microarchitecture-Aware Custom Instruction Design for RISC-V Processors
par: Rezunov, Evgenii, et autres
Publié: (2025)

Introducing Instruction-Accurate Simulators for Performance Estimation of Autotuning Workloads
par: Pelke, Rebecca, et autres
Publié: (2025)

TroLL: Exploiting Structural Similarities between Logic Locking and Hardware Trojans
par: Liu, Yuntao, et autres
Publié: (2023)

Utilizing Layout Effects for Analog Logic Locking
par: Aljafar, Muayad J., et autres
Publié: (2024)

NISTT: A Non-Intrusive SystemC-TLM 2.0 Tracing Tool
par: Bosbach, Nils, et autres
Publié: (2022)

Prime+Retouch: When Cache is Locked and Leaked
par: Lee, Jaehyuk, et autres
Publié: (2024)

TLGLock: A New Approach in Logic Locking Using Key-Driven Charge Recycling in Threshold Logic Gates
par: Sahruri, Abdullah, et autres
Publié: (2025)

TroLLoc: Logic Locking and Layout Hardening for IC Security Closure against Hardware Trojans
par: Wang, Fangzhou, et autres
Publié: (2024)

Robust and Attack Resilient Logic Locking with a High Application-Level Impact
par: Liu, Yuntao, et autres
Publié: (2021)

Fast-Locking and High-Resolution Mixed-Mode DLL with Binary Search and Clock Failure Detection for Wide Frequency Ranges in 3-nm FinFET CMOS
par: Wainstein, Nicolás, et autres
Publié: (2025)

QUADOL: A Quality-Driven Approximate Logic Synthesis Method Exploiting Dual-Output LUTs for Modern FPGAs
par: Shi, Jian, et autres
Publié: (2024)

parti-gem5: gem5's Timing Mode Parallelised
par: Cubero-Cascante, José, et autres
Publié: (2023)

Bridging the Gap: Physical PCI Device Integration Into SystemC-TLM Virtual Platforms
par: Bosbach, Nils, et autres
Publié: (2025)

Exploiting pre-optimized kernels with polyhedral transformations for CGRA compilation
par: Wang, Yuxuan, et autres
Publié: (2026)

ICP: Exploiting Instruction Correlation for Prefetching Irregular Memory Accesses
par: Li, Mengming, et autres
Publié: (2026)

Lumina: Real-Time Mobile Neural Rendering by Exploiting Computational Redundancy
par: Feng, Yu, et autres
Publié: (2025)

CLSA-CIM: A Cross-Layer Scheduling Approach for Computing-in-Memory Architectures
par: Pelke, Rebecca, et autres
Publié: (2024)

VUSA: Virtually Upscaled Systolic Array Architecture to Exploit Unstructured Sparsity in AI Acceleration
par: Helal, Shereef, et autres
Publié: (2025)

ResiLogic: Leveraging Composability and Diversity to Design Fault and Intrusion Resilient Chips
par: Sheikh, Ahmad T., et autres
Publié: (2024)

Asynchronous Memory Access Unit: Exploiting Massive Parallelism for Far Memory Access
par: Wang, Luming, et autres
Publié: (2024)

Exploiting Control-flow Enforcement Technology for Sound and Precise Static Binary Disassembly
par: Zhao, Brian, et autres
Publié: (2025)

DFModel: Design Space Optimization of Large-Scale Systems Exploiting Dataflow Mappings
par: Ko, Sho, et autres
Publié: (2024)

BARD: Reducing Write Latency of DDR5 Memory by Exploiting Bank-Parallelism
par: Vittal, Suhas, et autres
Publié: (2025)

Towards Efficient SRAM-PIM Architecture Design by Exploiting Unstructured Bit-Level Sparsity
par: Duan, Cenlin, et autres
Publié: (2024)

Conditional Flood Fill Method in Logic Synthesis
par: Yang, Shitian, et autres
Publié: (2023)

Functionality Locality, Mixture & Control = Logic = Memory
par: Peng, Xiangjun
Publié: (2024)

Squire: A General-Purpose Accelerator to Exploit Fine-Grain Parallelism on Dependency-Bound Kernels
par: Langarita, Rubén, et autres
Publié: (2025)

Leveraging Recurrent Patterns in Graph Accelerators
par: Rahimi, Masoud, et autres
Publié: (2025)

L-PCN: A Point Cloud Accelerator Exploiting Spatial Locality through Octree-based Islandization
par: Gao, Yiming, et autres
Publié: (2026)

FireFly-S: Exploiting Dual-Side Sparsity for Spiking Neural Networks Acceleration with Reconfigurable Spatial Architecture
par: Li, Tenglong, et autres
Publié: (2024)

Efficient CMOS Invertible Logic Using Stochastic Computing
par: Smithson, Sean C., et autres
Publié: (2026)

Interconnect-Aware Logic Resynthesis for Multi-Die FPGAs
par: Wang, Xiaoke, et autres
Publié: (2026)

Exploring and Exploiting Runtime Reconfigurable Floating Point Precision in Scientific Computing: a Case Study for Solving PDEs
par: Hao, Cong "Callie"
Publié: (2024)

SmaRTLy: RTL Optimization with Logic Inferencing and Structural Rebuilding
par: Li, Chengxi, et autres
Publié: (2025)

RTL Verification for Secure Speculation Using Contract Shadow Logic
par: Tan, Qinhan, et autres
Publié: (2024)

Small Logic-based Multipliers with Incomplete Sub-Multipliers for FPGAs
par: Böttcher, Andreas, et autres
Publié: (2024)

ML-based AIG Timing Prediction to Enhance Logic Optimization
par: Jiang, Wenjing, et autres
Publié: (2024)

DiSC: Resolution-Scalable Acceleration of Diffusion Models by Exploiting Sparsity and Cached Token Reuse with Hash-based Distribution
par: Yoon, Jieon, et autres
Publié: (2026)