ICGMM: CXL-enabled Memory Expansion with Intelligent Caching Using Gaussian Mixture Model
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arXiv
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| Autori principali: | , , , , , , , , , |
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| Natura: | Preprint |
| Pubblicazione: |
2024
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| _version_ | 1866910562891333632 |
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| author | Chen, Hanqiu Wang, Yitu Cargnini, Luis Vitorio Soltaniyeh, Mohammadreza Li, Dongyang Sun, Gongjin Subedi, Pradeep Chang, Andrew Chen, Yiran Hao, Cong |
| author_facet | Chen, Hanqiu Wang, Yitu Cargnini, Luis Vitorio Soltaniyeh, Mohammadreza Li, Dongyang Sun, Gongjin Subedi, Pradeep Chang, Andrew Chen, Yiran Hao, Cong |
| contents | Compute Express Link (CXL) emerges as a solution for wide gap between computational speed and data communication rates among host and multiple devices. It fosters a unified and coherent memory space between host and CXL storage devices such as such as Solid-state drive (SSD) for memory expansion, with a corresponding DRAM implemented as the device cache. However, this introduces challenges such as substantial cache miss penalties, sub-optimal caching due to data access granularity mismatch between the DRAM "cache" and SSD "memory", and inefficient hardware cache management. To address these issues, we propose a novel solution, named ICGMM, which optimizes caching and eviction directly on hardware, employing a Gaussian Mixture Model (GMM)-based approach. We prototype our solution on an FPGA board, which demonstrates a noteworthy improvement compared to the classic Least Recently Used (LRU) cache strategy. We observe a decrease in the cache miss rate ranging from 0.32% to 6.14%, leading to a substantial 16.23% to 39.14% reduction in the average SSD access latency. Furthermore, when compared to the state-of-the-art Long Short-Term Memory (LSTM)-based cache policies, our GMM algorithm on FPGA showcases an impressive latency reduction of over 10,000 times. Remarkably, this is achieved while demanding much fewer hardware resources. |
| format | Preprint |
| id |
arxiv_https___arxiv_org_abs_2408_05614 |
| institution | arXiv |
| publishDate | 2024 |
| record_format | arxiv |
| spellingShingle | ICGMM: CXL-enabled Memory Expansion with Intelligent Caching Using Gaussian Mixture Model Chen, Hanqiu Wang, Yitu Cargnini, Luis Vitorio Soltaniyeh, Mohammadreza Li, Dongyang Sun, Gongjin Subedi, Pradeep Chang, Andrew Chen, Yiran Hao, Cong Hardware Architecture Emerging Technologies Systems and Control Compute Express Link (CXL) emerges as a solution for wide gap between computational speed and data communication rates among host and multiple devices. It fosters a unified and coherent memory space between host and CXL storage devices such as such as Solid-state drive (SSD) for memory expansion, with a corresponding DRAM implemented as the device cache. However, this introduces challenges such as substantial cache miss penalties, sub-optimal caching due to data access granularity mismatch between the DRAM "cache" and SSD "memory", and inefficient hardware cache management. To address these issues, we propose a novel solution, named ICGMM, which optimizes caching and eviction directly on hardware, employing a Gaussian Mixture Model (GMM)-based approach. We prototype our solution on an FPGA board, which demonstrates a noteworthy improvement compared to the classic Least Recently Used (LRU) cache strategy. We observe a decrease in the cache miss rate ranging from 0.32% to 6.14%, leading to a substantial 16.23% to 39.14% reduction in the average SSD access latency. Furthermore, when compared to the state-of-the-art Long Short-Term Memory (LSTM)-based cache policies, our GMM algorithm on FPGA showcases an impressive latency reduction of over 10,000 times. Remarkably, this is achieved while demanding much fewer hardware resources. |
| title | ICGMM: CXL-enabled Memory Expansion with Intelligent Caching Using Gaussian Mixture Model |
| topic | Hardware Architecture Emerging Technologies Systems and Control |
| url | https://arxiv.org/abs/2408.05614 |