UFO-MAC: A Unified Framework for Optimization of High-Performance Multipliers and Multiply-Accumulators
Fuente:
arXiv
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| Main Authors: | Zuo, Dongsheng, Zhu, Jiadong, Li, Chenglin, Ma, Yuzhe |
|---|---|
| Format: | Preprint |
| Published: |
2024
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| Subjects: | |
| Online Access: | |
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