A 1.6-fJ/Spike Subthreshold Analog Spiking Neuron in 28 nm CMOS
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arXiv
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| Format: | Preprint |
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2024
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| author | Besrour, Marwan Omrani, Takwa Lavoie, Jacob Martin-Hardy, Gabriel Koleibi, Esmaeil Ranjbar Menard, Jeremy Koua, Konin Marcoux, Philippe Boukadoum, Mounir Fontaine, Rejean |
| author_facet | Besrour, Marwan Omrani, Takwa Lavoie, Jacob Martin-Hardy, Gabriel Koleibi, Esmaeil Ranjbar Menard, Jeremy Koua, Konin Marcoux, Philippe Boukadoum, Mounir Fontaine, Rejean |
| contents | The computational complexity of deep learning algorithms has given rise to significant speed and memory challenges for the execution hardware. In energy-limited portable devices, highly efficient processing platforms are indispensable for reproducing the prowess afforded by much bulkier processing platforms.
In this work, we present a low-power Leaky Integrate-and-Fire (LIF) neuron design fabricated in TSMC's 28 nm CMOS technology as proof of concept to build an energy-efficient mixed-signal Neuromorphic System-on-Chip (NeuroSoC). The fabricated neuron consumes 1.61 fJ/spike and occupies an active area of 34 $μm^{2}$, leading to a maximum spiking frequency of 300 kHz at 250 mV power supply.
These performances are used in a software model to emulate the dynamics of a Spiking Neural Network (SNN). Employing supervised backpropagation and a surrogate gradient technique, the resulting accuracy on the MNIST dataset, using 4-bit post-training quantization stands at 82.5\%. The approach underscores the potential of such ASIC implementation of quantized SNNs to deliver high-performance, energy-efficient solutions to various embedded machine-learning applications. |
| format | Preprint |
| id |
arxiv_https___arxiv_org_abs_2408_07734 |
| institution | arXiv |
| publishDate | 2024 |
| record_format | arxiv |
| spellingShingle | A 1.6-fJ/Spike Subthreshold Analog Spiking Neuron in 28 nm CMOS Besrour, Marwan Omrani, Takwa Lavoie, Jacob Martin-Hardy, Gabriel Koleibi, Esmaeil Ranjbar Menard, Jeremy Koua, Konin Marcoux, Philippe Boukadoum, Mounir Fontaine, Rejean Neural and Evolutionary Computing Signal Processing The computational complexity of deep learning algorithms has given rise to significant speed and memory challenges for the execution hardware. In energy-limited portable devices, highly efficient processing platforms are indispensable for reproducing the prowess afforded by much bulkier processing platforms. In this work, we present a low-power Leaky Integrate-and-Fire (LIF) neuron design fabricated in TSMC's 28 nm CMOS technology as proof of concept to build an energy-efficient mixed-signal Neuromorphic System-on-Chip (NeuroSoC). The fabricated neuron consumes 1.61 fJ/spike and occupies an active area of 34 $μm^{2}$, leading to a maximum spiking frequency of 300 kHz at 250 mV power supply. These performances are used in a software model to emulate the dynamics of a Spiking Neural Network (SNN). Employing supervised backpropagation and a surrogate gradient technique, the resulting accuracy on the MNIST dataset, using 4-bit post-training quantization stands at 82.5\%. The approach underscores the potential of such ASIC implementation of quantized SNNs to deliver high-performance, energy-efficient solutions to various embedded machine-learning applications. |
| title | A 1.6-fJ/Spike Subthreshold Analog Spiking Neuron in 28 nm CMOS |
| topic | Neural and Evolutionary Computing Signal Processing |
| url | https://arxiv.org/abs/2408.07734 |