Cross-Chip Partial Reconfiguration for the Initialisation of Modular and Scalable Heterogeneous Systems
Fuente:
arXiv
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| Autori principali: | , , , , , |
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| Natura: | Preprint |
| Pubblicazione: |
2024
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| _version_ | 1866913469583851520 |
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| author | Fuchs, Marvin Krause, Hendrik Muscheid, Timo Scheller, Lukas Ardila-Perez, Luis E. Sander, Oliver |
| author_facet | Fuchs, Marvin Krause, Hendrik Muscheid, Timo Scheller, Lukas Ardila-Perez, Luis E. Sander, Oliver |
| contents | The almost unlimited possibilities to customize the logic in an FPGA are one of the main reasons for the versatility of these devices. Partial reconfiguration exploits this capability even further by allowing to replace logic in predefined FPGA regions at runtime. This is especially relevant in heterogeneous SoCs, combining FPGA fabric with conventional processors on a single die. Tight integration and supporting frameworks like the FPGA subsystem in Linux facilitate use, for example, to dynamically load custom hardware accelerators. Although this example is one of the most common use cases for partial reconfiguration, the possible applications go far beyond. We propose to use partial reconfiguration in combination with the AXI C2C cross-chip bus to extend the resources of heterogeneous MPSoC and RFSoC devices by connecting peripheral FPGAs. With AXI C2C it is easily possible to link the programmable logic of the individual devices, but partial reconfiguration on peripheral FPGAs utilising the same channel is not officially supported. By using an AXI ICAP controller in combination with custom Linux drivers, we show that it is possible to enable the PS of the heterogeneous SoC to perform partial reconfiguration on peripheral FPGAs, and thus to seamlessly access and manage the entire multi-device system. As a result, software and FPGA firmware updates can be applied to the entire system at runtime, and peripheral FPGAs can be added and removed during operation. |
| format | Preprint |
| id |
arxiv_https___arxiv_org_abs_2408_08626 |
| institution | arXiv |
| publishDate | 2024 |
| record_format | arxiv |
| spellingShingle | Cross-Chip Partial Reconfiguration for the Initialisation of Modular and Scalable Heterogeneous Systems Fuchs, Marvin Krause, Hendrik Muscheid, Timo Scheller, Lukas Ardila-Perez, Luis E. Sander, Oliver Instrumentation and Detectors Systems and Control The almost unlimited possibilities to customize the logic in an FPGA are one of the main reasons for the versatility of these devices. Partial reconfiguration exploits this capability even further by allowing to replace logic in predefined FPGA regions at runtime. This is especially relevant in heterogeneous SoCs, combining FPGA fabric with conventional processors on a single die. Tight integration and supporting frameworks like the FPGA subsystem in Linux facilitate use, for example, to dynamically load custom hardware accelerators. Although this example is one of the most common use cases for partial reconfiguration, the possible applications go far beyond. We propose to use partial reconfiguration in combination with the AXI C2C cross-chip bus to extend the resources of heterogeneous MPSoC and RFSoC devices by connecting peripheral FPGAs. With AXI C2C it is easily possible to link the programmable logic of the individual devices, but partial reconfiguration on peripheral FPGAs utilising the same channel is not officially supported. By using an AXI ICAP controller in combination with custom Linux drivers, we show that it is possible to enable the PS of the heterogeneous SoC to perform partial reconfiguration on peripheral FPGAs, and thus to seamlessly access and manage the entire multi-device system. As a result, software and FPGA firmware updates can be applied to the entire system at runtime, and peripheral FPGAs can be added and removed during operation. |
| title | Cross-Chip Partial Reconfiguration for the Initialisation of Modular and Scalable Heterogeneous Systems |
| topic | Instrumentation and Detectors Systems and Control |
| url | https://arxiv.org/abs/2408.08626 |