In-Memory Learning Automata Architecture using Y-Flash Cell
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arXiv
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| Autores principales: | , , , , , |
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| Formato: | Preprint |
| Publicado: |
2024
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| _version_ | 1866913471092752384 |
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| author | Ghazal, Omar Lan, Tian Ojukwu, Shalman Krishnamurthy, Komal Yakovlev, Alex Shafik, Rishad |
| author_facet | Ghazal, Omar Lan, Tian Ojukwu, Shalman Krishnamurthy, Komal Yakovlev, Alex Shafik, Rishad |
| contents | The modern implementation of machine learning architectures faces significant challenges due to frequent data transfer between memory and processing units. In-memory computing, primarily through memristor-based analog computing, offers a promising solution to overcome this von Neumann bottleneck. In this technology, data processing and storage are located inside the memory. Here, we introduce a novel approach that utilizes floating-gate Y-Flash memristive devices manufactured with a standard 180 nm CMOS process. These devices offer attractive features, including analog tunability and moderate device-to-device variation; such characteristics are essential for reliable decision-making in ML applications. This paper uses a new machine learning algorithm, the Tsetlin Machine (TM), for in-memory processing architecture. The TM's learning element, Automaton, is mapped into a single Y-Flash cell, where the Automaton's range is transferred into the Y-Flash's conductance scope. Through comprehensive simulations, the proposed hardware implementation of the learning automata, particularly for Tsetlin machines, has demonstrated enhanced scalability and on-edge learning capabilities. |
| format | Preprint |
| id |
arxiv_https___arxiv_org_abs_2408_09456 |
| institution | arXiv |
| publishDate | 2024 |
| record_format | arxiv |
| spellingShingle | In-Memory Learning Automata Architecture using Y-Flash Cell Ghazal, Omar Lan, Tian Ojukwu, Shalman Krishnamurthy, Komal Yakovlev, Alex Shafik, Rishad Hardware Architecture Artificial Intelligence Emerging Technologies Machine Learning The modern implementation of machine learning architectures faces significant challenges due to frequent data transfer between memory and processing units. In-memory computing, primarily through memristor-based analog computing, offers a promising solution to overcome this von Neumann bottleneck. In this technology, data processing and storage are located inside the memory. Here, we introduce a novel approach that utilizes floating-gate Y-Flash memristive devices manufactured with a standard 180 nm CMOS process. These devices offer attractive features, including analog tunability and moderate device-to-device variation; such characteristics are essential for reliable decision-making in ML applications. This paper uses a new machine learning algorithm, the Tsetlin Machine (TM), for in-memory processing architecture. The TM's learning element, Automaton, is mapped into a single Y-Flash cell, where the Automaton's range is transferred into the Y-Flash's conductance scope. Through comprehensive simulations, the proposed hardware implementation of the learning automata, particularly for Tsetlin machines, has demonstrated enhanced scalability and on-edge learning capabilities. |
| title | In-Memory Learning Automata Architecture using Y-Flash Cell |
| topic | Hardware Architecture Artificial Intelligence Emerging Technologies Machine Learning |
| url | https://arxiv.org/abs/2408.09456 |