Security Risks Due to Data Persistence in Cloud FPGA Platforms
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arXiv
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| Auteurs principaux: | , , , |
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| Format: | Preprint |
| Publié: |
2024
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| _version_ | 1866929465610731520 |
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| author | Zhang, Zhehang Madabhushi, Bharadwaj Kundu, Sandip Tessier, Russell |
| author_facet | Zhang, Zhehang Madabhushi, Bharadwaj Kundu, Sandip Tessier, Russell |
| contents | The integration of Field Programmable Gate Arrays (FPGAs) into cloud computing systems has become commonplace. As the operating systems used to manage these systems evolve, special consideration must be given to DRAM devices accessible by FPGAs. These devices may hold sensitive data that can become inadvertently exposed to adversaries following user logout. Although addressed in some cloud FPGA environments, automatic DRAM clearing after process termination is not automatically included in popular FPGA runtime environments nor in most proposed cloud FPGA hypervisors. In this paper, we examine DRAM data persistence in AMD/Xilinx Alveo U280 nodes that are part of the Open Cloud Testbed (OCT). Our results indicate that DDR4 DRAM is not automatically cleared following user logout from an allocated node and subsequent node users can easily obtain recognizable data from the DRAM following node reallocation over 17 minutes later. This issue is particularly relevant for systems which support FPGA multi-tenancy. |
| format | Preprint |
| id |
arxiv_https___arxiv_org_abs_2408_10374 |
| institution | arXiv |
| publishDate | 2024 |
| record_format | arxiv |
| spellingShingle | Security Risks Due to Data Persistence in Cloud FPGA Platforms Zhang, Zhehang Madabhushi, Bharadwaj Kundu, Sandip Tessier, Russell Cryptography and Security Hardware Architecture Distributed, Parallel, and Cluster Computing The integration of Field Programmable Gate Arrays (FPGAs) into cloud computing systems has become commonplace. As the operating systems used to manage these systems evolve, special consideration must be given to DRAM devices accessible by FPGAs. These devices may hold sensitive data that can become inadvertently exposed to adversaries following user logout. Although addressed in some cloud FPGA environments, automatic DRAM clearing after process termination is not automatically included in popular FPGA runtime environments nor in most proposed cloud FPGA hypervisors. In this paper, we examine DRAM data persistence in AMD/Xilinx Alveo U280 nodes that are part of the Open Cloud Testbed (OCT). Our results indicate that DDR4 DRAM is not automatically cleared following user logout from an allocated node and subsequent node users can easily obtain recognizable data from the DRAM following node reallocation over 17 minutes later. This issue is particularly relevant for systems which support FPGA multi-tenancy. |
| title | Security Risks Due to Data Persistence in Cloud FPGA Platforms |
| topic | Cryptography and Security Hardware Architecture Distributed, Parallel, and Cluster Computing |
| url | https://arxiv.org/abs/2408.10374 |