System-Level Design Space Exploration for High-Level Synthesis under End-to-End Latency Constraints

Fuente: arXiv

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Bibliographic Details
Main Authors:	Liao, Yuchao, Adegbija, Tosiron, Lysecky, Roman
Format:	Preprint
Published:	2024
Subjects:	Hardware Architecture
Online Access:	Acceder al recurso
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Internet

https://arxiv.org/abs/2408.10431