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System-Level Design Space Exploration for High-Level Synthesis under End-to-End Latency Constraints

Fuente: arXiv

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Détails bibliographiques
Auteurs principaux:	Liao, Yuchao, Adegbija, Tosiron, Lysecky, Roman
Format:	Preprint
Publié:	2024
Sujets:	Hardware Architecture
Accès en ligne:	Acceder al recurso
Tags:	Ajouter un tag Pas de tags, Soyez le premier à ajouter un tag!

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