Design and Implementation of a Takum Arithmetic Hardware Codec
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arXiv
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| Format: | Preprint |
| Published: |
2024
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| _version_ | 1866917104284860416 |
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| author | Hunhold, Laslo |
| author_facet | Hunhold, Laslo |
| contents | The takum machine number format has been recently proposed as an enhancement over the posit number format, which is considered a promising alternative to the IEEE 754 floating-point standard. Takums retain the useful posit properties, but feature a novel exponent coding scheme that yields more precision for small and large magnitude numbers and a much higher and bounded dynamic range.
This paper presents the design and implementation of a hardware codec for both takums (logarithmic number system, LNS) and linear takums (floating-point format). The codec design is emphasised, as it constitutes the primary distinguishing feature compared to logarithmic posits (LNS) and posits (floating-point format), which otherwise share similar internal representations. Furthermore, a novel internal representation for LNS is proposed. The presented takum codec, implemented in VHDL, demonstrates near-optimal scalability and performance on an FPGA. It achieves latency reductions of up to 38% and reduces LUT utilisation up to 50% compared to the best state-of-the-art posit codecs. |
| format | Preprint |
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arxiv_https___arxiv_org_abs_2408_10594 |
| institution | arXiv |
| publishDate | 2024 |
| record_format | arxiv |
| spellingShingle | Design and Implementation of a Takum Arithmetic Hardware Codec Hunhold, Laslo Hardware Architecture 68M07 B.2.1; B.2.2 The takum machine number format has been recently proposed as an enhancement over the posit number format, which is considered a promising alternative to the IEEE 754 floating-point standard. Takums retain the useful posit properties, but feature a novel exponent coding scheme that yields more precision for small and large magnitude numbers and a much higher and bounded dynamic range. This paper presents the design and implementation of a hardware codec for both takums (logarithmic number system, LNS) and linear takums (floating-point format). The codec design is emphasised, as it constitutes the primary distinguishing feature compared to logarithmic posits (LNS) and posits (floating-point format), which otherwise share similar internal representations. Furthermore, a novel internal representation for LNS is proposed. The presented takum codec, implemented in VHDL, demonstrates near-optimal scalability and performance on an FPGA. It achieves latency reductions of up to 38% and reduces LUT utilisation up to 50% compared to the best state-of-the-art posit codecs. |
| title | Design and Implementation of a Takum Arithmetic Hardware Codec |
| topic | Hardware Architecture 68M07 B.2.1; B.2.2 |
| url | https://arxiv.org/abs/2408.10594 |