CGRA4ML: A Hardware/Software Framework to Implement Neural Networks for Scientific Edge Computing
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arXiv
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| Autori principali: | , , , , |
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| Natura: | Preprint |
| Pubblicazione: |
2024
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| _version_ | 1866908915915030528 |
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| author | Abarajithan, G Ma, Zhenghua Munasinghe, Ravidu Restuccia, Francesco Kastner, Ryan |
| author_facet | Abarajithan, G Ma, Zhenghua Munasinghe, Ravidu Restuccia, Francesco Kastner, Ryan |
| contents | The scientific community increasingly relies on machine learning (ML) for near-sensor processing, leveraging its strengths in tasks such as pattern recognition, anomaly detection, and real-time decision-making. These deployments demand accelerators that combine extremely high performance with programmability, ease of integration, and straightforward verification. We present cgra4ml, an open-source, modular framework that generates parameterizable CGRA accelerators in synthesizable SystemVerilog RTL, tailored to common ML compute patterns found in scientific applications. The framework supports seamless system integration through AXI-compliant interfaces and open-source DMA components, and it includes automatic firmware generation for programming the accelerator. A comprehensive verification suite and a runtime firmware stack further support deployment across diverse SoC platforms. cgra4ml provides a modular, full-stack infrastructure, including a Python API, SystemVerilog hardware, TCL toolflows, and a C runtime, which facilitates easy integration and experimentation, allowing scientists to focus on innovation rather than dealing with the intricacies of hardware design and optimization. We demonstrate the effectiveness of cgra4ml to implement common scientific edge neural networks using ASIC and FPGA design flows. |
| format | Preprint |
| id |
arxiv_https___arxiv_org_abs_2408_15561 |
| institution | arXiv |
| publishDate | 2024 |
| record_format | arxiv |
| spellingShingle | CGRA4ML: A Hardware/Software Framework to Implement Neural Networks for Scientific Edge Computing Abarajithan, G Ma, Zhenghua Munasinghe, Ravidu Restuccia, Francesco Kastner, Ryan Hardware Architecture Artificial Intelligence 68T07, 68U01, 65Y05 B.7.1; C.1.3 The scientific community increasingly relies on machine learning (ML) for near-sensor processing, leveraging its strengths in tasks such as pattern recognition, anomaly detection, and real-time decision-making. These deployments demand accelerators that combine extremely high performance with programmability, ease of integration, and straightforward verification. We present cgra4ml, an open-source, modular framework that generates parameterizable CGRA accelerators in synthesizable SystemVerilog RTL, tailored to common ML compute patterns found in scientific applications. The framework supports seamless system integration through AXI-compliant interfaces and open-source DMA components, and it includes automatic firmware generation for programming the accelerator. A comprehensive verification suite and a runtime firmware stack further support deployment across diverse SoC platforms. cgra4ml provides a modular, full-stack infrastructure, including a Python API, SystemVerilog hardware, TCL toolflows, and a C runtime, which facilitates easy integration and experimentation, allowing scientists to focus on innovation rather than dealing with the intricacies of hardware design and optimization. We demonstrate the effectiveness of cgra4ml to implement common scientific edge neural networks using ASIC and FPGA design flows. |
| title | CGRA4ML: A Hardware/Software Framework to Implement Neural Networks for Scientific Edge Computing |
| topic | Hardware Architecture Artificial Intelligence 68T07, 68U01, 65Y05 B.7.1; C.1.3 |
| url | https://arxiv.org/abs/2408.15561 |