FireFly-S: Exploiting Dual-Side Sparsity for Spiking Neural Networks Acceleration with Reconfigurable Spatial Architecture
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arXiv
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| Main Authors: | Li, Tenglong, Li, Jindong, Shen, Guobin, Zhao, Dongcheng, Zhang, Qian, Zeng, Yi |
|---|---|
| Format: | Preprint |
| Published: |
2024
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| Subjects: | |
| Online Access: | |
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