PC-Indexed Data Address Translation
Fuente:
arXiv
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| Autori principali: | , |
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| Natura: | Preprint |
| Pubblicazione: |
2024
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| _version_ | 1866912992837238784 |
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| author | Murthy, Shyam Sohi, Gurindar S |
| author_facet | Murthy, Shyam Sohi, Gurindar S |
| contents | This paper proposes a novel way to assist conventional data address translation. The approach, PC-Indexed Data Address Translation (PCAX), uses the PC of a load instruction, and not a data virtual address, to obtain the page table entry (PTE) for the data accessed by a load instruction. PCAX is intended to be used for a small subset of the static loads in a program. We observe that: (i) a small subset of static loads is responsible for most of the misses in a data translation lookaside buffer (DTLB), and (ii) often a dynamic instance of a static load instruction accesses the same PTE as the last dynamic instance, and consider PCAX for this subset. With PCAX the effective miss rate of a conventional DTLB can be cut down by a factor of 2-3X in many cases, and even more in some cases. PCAX is also beneficial in reducing the number of secondary TLB (STLB) misses. Since the tables used for PCAX can be accessed alongside instruction fetch, they can be slow, yet frequently provide a valid PTE even before the data address calculation. This yields an average performance improvement of 1.7% while reducing data address translation energy by 7% across 84 server traces. |
| format | Preprint |
| id |
arxiv_https___arxiv_org_abs_2408_15878 |
| institution | arXiv |
| publishDate | 2024 |
| record_format | arxiv |
| spellingShingle | PC-Indexed Data Address Translation Murthy, Shyam Sohi, Gurindar S Hardware Architecture This paper proposes a novel way to assist conventional data address translation. The approach, PC-Indexed Data Address Translation (PCAX), uses the PC of a load instruction, and not a data virtual address, to obtain the page table entry (PTE) for the data accessed by a load instruction. PCAX is intended to be used for a small subset of the static loads in a program. We observe that: (i) a small subset of static loads is responsible for most of the misses in a data translation lookaside buffer (DTLB), and (ii) often a dynamic instance of a static load instruction accesses the same PTE as the last dynamic instance, and consider PCAX for this subset. With PCAX the effective miss rate of a conventional DTLB can be cut down by a factor of 2-3X in many cases, and even more in some cases. PCAX is also beneficial in reducing the number of secondary TLB (STLB) misses. Since the tables used for PCAX can be accessed alongside instruction fetch, they can be slow, yet frequently provide a valid PTE even before the data address calculation. This yields an average performance improvement of 1.7% while reducing data address translation energy by 7% across 84 server traces. |
| title | PC-Indexed Data Address Translation |
| topic | Hardware Architecture |
| url | https://arxiv.org/abs/2408.15878 |