Image de couverture de livre

DeTRAP: RISC-V Return Address Protection With Debug Triggers

Fuente: arXiv

Enregistré dans:

Détails bibliographiques
Auteurs principaux:	Richter, Isaac, Zhou, Jie, Criswell, John
Format:	Preprint
Publié:	2024
Sujets:	Cryptography and Security
Accès en ligne:	Acceder al recurso
Tags:	Ajouter un tag Pas de tags, Soyez le premier à ajouter un tag!

Documents similaires

Fast Summary-based Whole-program Analysis to Identify Unsafe Memory Accesses in Rust
par: Zhou, Jie, et autres
Publié: (2023)

CryptRISC: A Secure RISC-V Processor for High-Performance Cryptography with Power Side-Channel Protection
par: Srivastava, Amisha, et autres
Publié: (2026)

ACE: Confidential Computing for Embedded RISC-V Systems
par: Ozga, Wojciech, et autres
Publié: (2025)

Dorami: Privilege Separating Security Monitor on RISC-V TEEs
par: Kuhne, Mark, et autres
Publié: (2024)

Systematic Assessment of Cache Timing Vulnerabilities on RISC-V Processors
par: Austa, Cédrick, et autres
Publié: (2025)

TRAP: Hijacking VLA CoT-Reasoning via Adversarial Patches
par: Huang, Zhengxian, et autres
Publié: (2026)

Hardware-based stack buffer overflow attack detection on RISC-V architectures
par: Chenet, Cristiano Pegoraro, et autres
Publié: (2024)

Synthesizing Hardware-Software Leakage Contracts for RISC-V Open-Source Processors
par: Mohr, Gideon, et autres
Publié: (2024)

Synthesis of Sound and Precise Leakage Contracts for Open-Source RISC-V Processors
par: Wang, Zilong, et autres
Publié: (2025)

On Securing the Software Development Lifecycle in IoT RISC-V Trusted Execution Environments
par: Wilde, Annika, et autres
Publié: (2026)

Safe Sharing of Fast Kernel-Bypass I/O Among Nontrusting Applications
par: Beadle, Alan, et autres
Publié: (2025)

RISecure-PUF: Multipurpose PUF-Driven Security Extensions with Lookaside Buffer in RISC-V
par: Chen, Chenghao, et autres
Publié: (2024)

R5Detect: Detecting Control-Flow Attacks from Standard RISC-V Enclaves
par: Bove, Davide, et autres
Publié: (2024)

Branch Landing: Bloom Filter-Based Source Authorization for Forward-Edge CFI on RISC-V
par: Wu, You, et autres
Publié: (2026)

External entropy supply for IoT devices employing a RISC-V Trusted Execution Environment
par: Paju, Arttu, et autres
Publié: (2026)

RISC-V Needs Secure 'Wheels': the MCU Initiator-Side Perspective
par: Pinto, Sandro, et autres
Publié: (2024)

SimFuzz: Similarity-guided Block-level Mutation for RISC-V Processor Fuzzing
par: Lyu, Hao, et autres
Publié: (2026)

SAILOR: A Scalable and Energy-Efficient Ultra-Lightweight RISC-V for IoT Security
par: Ewert, Christian, et autres
Publié: (2026)

PermuteV: A Performant Side-channel-Resistant RISC-V Core Securing Edge AI Inference
par: Narkthong, Nuntipat, et autres
Publié: (2025)

Translating Common Security Assertions Across Processor Designs: A RISC-V Case Study
par: Imtiaz, Sharjeel, et autres
Publié: (2025)

CVA6-CFI: A First Glance at RISC-V Control-Flow Integrity Extensions
par: Manoni, Simone, et autres
Publié: (2026)

LogJack: Indirect Prompt Injection Through Cloud Logs Against LLM Debugging Agents
par: Shah, Harsh
Publié: (2026)

System-Level Isolation for Mixed-Criticality RISC-V SoCs: A "World" Reality Check
par: Cunha, Luis, et autres
Publié: (2026)

Crypto-RV: High-Efficiency FPGA-Based RISC-V Cryptographic Co-Processor for IoT Security
par: Pham, Anh Kiet, et autres
Publié: (2026)

Power Side-Channel Analysis of the CVA6 RISC-V Core at the RTL Level Using VeriSide
par: Farnaghinejad, Behnam, et autres
Publié: (2025)

Protecting DeFi Platforms against Non-Price Flash Loan Attacks
par: Alhaidari, Abdulrahman, et autres
Publié: (2025)

Blockchain Address Poisoning
par: Tsuchiya, Taro, et autres
Publié: (2025)

NanoZone: Scalable, Efficient, and Secure Memory Protection for Arm CCA
par: Liu, Shiqi, et autres
Publié: (2025)

The Elusive Pursuit of Reproducing PATE-GAN: Benchmarking, Auditing, Debugging
par: Ganev, Georgi, et autres
Publié: (2024)

ModelObfuscator: Obfuscating Model Information to Protect Deployed ML-based Systems
par: Zhou, Mingyi, et autres
Publié: (2023)

HeisenTrojans: They Are Not There Until They Are Triggered
par: Mavurapu, Akshita Reddy, et autres
Publié: (2023)

CoTGuard: Using Chain-of-Thought Triggering for Copyright Protection in Multi-Agent LLM Systems
par: Wen, Yan, et autres
Publié: (2025)

DRsam: Detection of Fault-Based Microarchitectural Side-Channel Attacks in RISC-V Using Statistical Preprocessing and Association Rule Mining
par: Hassan, Muhammad, et autres
Publié: (2025)

RegionMarker: A Region-Triggered Semantic Watermarking Framework for Embedding-as-a-Service Copyright Protection
par: Yang, Shufan, et autres
Publié: (2025)

More Efficient Stealth Address Protocol
par: Mikic, Marija, et autres
Publié: (2025)

Post-Quantum Stealth Address Protocols
par: Mikic, Marija, et autres
Publié: (2025)

Microarchitecture Design and Benchmarking of Custom SHA-3 Instruction for RISC-V
par: Bolat, Alperen, et autres
Publié: (2025)

AquaLoRA: Toward White-box Protection for Customized Stable Diffusion Models via Watermark LoRA
par: Feng, Weitao, et autres
Publié: (2024)

Bicoptor 2.0: Addressing Challenges in Probabilistic Truncation for Enhanced Privacy-Preserving Machine Learning
par: Zhou, Lijing, et autres
Publié: (2023)

Elliptic Curve Pairing Stealth Address Protocols
par: Mikic, Marija, et autres
Publié: (2023)