TimeFloats: Train-in-Memory with Time-Domain Floating-Point Scalar Products
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arXiv
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| Hauptverfasser: | , , , , |
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| Format: | Preprint |
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2024
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| _version_ | 1866917848422547456 |
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| author | Hashem, Maeesha Binte Parpillon, Benjamin Kumar, Divake Jayasuria, Dinithi Trivedi, Amit Ranjan |
| author_facet | Hashem, Maeesha Binte Parpillon, Benjamin Kumar, Divake Jayasuria, Dinithi Trivedi, Amit Ranjan |
| contents | In this work, we propose "TimeFloats," an efficient train-in-memory architecture that performs 8-bit floating-point scalar product operations in the time domain. While building on the compute-in-memory paradigm's integrated storage and inferential computations, TimeFloats additionally enables floating-point computations, thus facilitating DNN training within the same memory structures. Traditional compute-in-memory approaches with conventional ADCs and DACs face challenges such as higher power consumption and increased design complexity, especially at advanced CMOS nodes. In contrast, TimeFloats leverages time-domain signal processing to avoid conventional domain converters. It operates predominantly with digital building blocks, reducing power consumption and noise sensitivity while enabling high-resolution computations and easier integration with conventional digital circuits. Our simulation results demonstrate an energy efficiency of 22.1 TOPS/W while evaluating the design on 15 nm CMOS technology. |
| format | Preprint |
| id |
arxiv_https___arxiv_org_abs_2409_00495 |
| institution | arXiv |
| publishDate | 2024 |
| record_format | arxiv |
| spellingShingle | TimeFloats: Train-in-Memory with Time-Domain Floating-Point Scalar Products Hashem, Maeesha Binte Parpillon, Benjamin Kumar, Divake Jayasuria, Dinithi Trivedi, Amit Ranjan Hardware Architecture In this work, we propose "TimeFloats," an efficient train-in-memory architecture that performs 8-bit floating-point scalar product operations in the time domain. While building on the compute-in-memory paradigm's integrated storage and inferential computations, TimeFloats additionally enables floating-point computations, thus facilitating DNN training within the same memory structures. Traditional compute-in-memory approaches with conventional ADCs and DACs face challenges such as higher power consumption and increased design complexity, especially at advanced CMOS nodes. In contrast, TimeFloats leverages time-domain signal processing to avoid conventional domain converters. It operates predominantly with digital building blocks, reducing power consumption and noise sensitivity while enabling high-resolution computations and easier integration with conventional digital circuits. Our simulation results demonstrate an energy efficiency of 22.1 TOPS/W while evaluating the design on 15 nm CMOS technology. |
| title | TimeFloats: Train-in-Memory with Time-Domain Floating-Point Scalar Products |
| topic | Hardware Architecture |
| url | https://arxiv.org/abs/2409.00495 |