Cover Image

ResiLogic: Leveraging Composability and Diversity to Design Fault and Intrusion Resilient Chips

Fuente: arXiv

Saved in:

Bibliographic Details
Main Authors:	Sheikh, Ahmad T., Shoker, Ali, Fahmy, Suhaib A., Esteves-Verissimo, Paulo
Format:	Preprint
Published:	2024
Subjects:	Cryptography and Security Hardware Architecture
Online Access:	Acceder al recurso
Tags:	Add Tag No Tags, Be the first to tag this record!

Similar Items

Resilient and Secure Programmable System-on-Chip Accelerator Offload
by: Gouveia, Inês Pinto, et al.
Published: (2024)

Trojan-Resilient NTT: Protecting Against Control Flow and Timing Faults on Reconfigurable Platforms
by: Paul, Rourab, et al.
Published: (2026)

Honest to a Fault: Root-Causing Fault Attacks with Pre-Silicon RISC Pipeline Characterization
by: Malik, Arsalan Ali, et al.
Published: (2025)

Evaluation of isolation design flow (IDF) for Single Chip Cryptography (SCC) application
by: Malik, Arsalan Ali
Published: (2025)

iThermTroj: Exploiting Intermittent Thermal Trojans in Multi-Processor System-on-Chips
by: Elahi, Mehdi, et al.
Published: (2025)

Exploiting the Lock: Leveraging MiG-V's Logic Locking for Secret-Data Extraction
by: Reimann, Lennart M., et al.
Published: (2024)

CRAFT: Characterizing and Root-Causing Fault Injection Threats at Pre-Silicon
by: Malik, Arsalan Ali, et al.
Published: (2025)

MATTER: Multi-stage Adaptive Thermal Trojan for Efficiency & Resilience degradation
by: Elahi, Mehdi, et al.
Published: (2024)

Automated Physical Design Watermarking Leveraging Graph Neural Networks
by: Zhang, Ruisi, et al.
Published: (2024)

RowPress Vulnerability in Modern DRAM Chips
by: Luo, Haocong, et al.
Published: (2024)

RowPress: Amplifying Read Disturbance in Modern DRAM Chips
by: Luo, Haocong, et al.
Published: (2023)

Secure Software/Hardware Hybrid In-Field Testing for System-on-Chip
by: Mulhem, Saleh, et al.
Published: (2024)

An Experimental Characterization of Combined RowHammer and RowPress Read Disturbance in Modern DRAM Chips
by: Luo, Haocong, et al.
Published: (2024)

Logic Encryption: This Time for Real
by: Karn, Rupesh Raj, et al.
Published: (2025)

ColumnDisturb: Understanding Column-based Read Disturbance in Real DRAM Chips and Implications for Future Systems
by: Yüksel, İsmail Emir, et al.
Published: (2025)

DiscoRD: An Experimental Methodology for Quickly Discovering the Reliable Read Disturbance Threshold of Real DRAM Chips
by: Olgun, Ataberk, et al.
Published: (2026)

DRAM Bender: An Extensible and Versatile FPGA-based Infrastructure to Easily Test State-of-the-art DRAM Chips
by: Olgun, Ataberk, et al.
Published: (2022)

PuDHammer: Experimental Analysis of Read Disturbance Effects of Processing-using-DRAM in Real DRAM Chips
by: Yuksel, Ismail Emir, et al.
Published: (2025)

SCARF: Securing Chips with a Robust Framework against Fabrication-time Hardware Trojans
by: Eslami, Mohammad, et al.
Published: (2024)

Utilizing Layout Effects for Analog Logic Locking
by: Aljafar, Muayad J., et al.
Published: (2024)

The Impact of Logic Locking on Confidentiality: An Automated Evaluation
by: Reimann, Lennart M., et al.
Published: (2025)

Laser Fault Injection Attacks against Radiation Tolerant TMR Registers
by: Petryk, Dmytro, et al.
Published: (2024)

Reliability Analysis of Fully Homomorphic Encryption Systems Under Memory Faults
by: Rajagede, Rian Adam, et al.
Published: (2025)

Understanding RowHammer Under Reduced Refresh Latency: Experimental Analysis of Real DRAM Chips and Implications on Future Solutions
by: Tuğrul, Yahya Can, et al.
Published: (2025)

Read Disturbance in High Bandwidth Memory: A Detailed Experimental Study on HBM2 DRAM Chips
by: Olgun, Ataberk, et al.
Published: (2023)

On the Influence of the Laser Illumination on the Logic Cells Current Consumption
by: Petryk, Dmytro, et al.
Published: (2024)

Spatial Variation-Aware Read Disturbance Defenses: Experimental Analysis of Real DRAM Chips and Implications on Future Solutions
by: Yağlıkçı, Abdullah Giray, et al.
Published: (2024)

Enabling Efficient and Scalable DRAM Read Disturbance Mitigation via New Experimental Insights into Modern DRAM Chips
by: Yağlıkçı, Abdullah Giray
Published: (2024)

Attacking AI Accelerators by Leveraging Arithmetic Properties of Addition
by: Heidary, Masoud, et al.
Published: (2026)

Leveraging ASIC AI Chips for Homomorphic Encryption
by: Tong, Jianming, et al.
Published: (2025)

SynFuzz: Leveraging Fuzzing of Netlist to Detect Synthesis Bugs
by: Saravanan, Raghul, et al.
Published: (2025)

TroLL: Exploiting Structural Similarities between Logic Locking and Hardware Trojans
by: Liu, Yuntao, et al.
Published: (2023)

Leveraging FPGAs for Homomorphic Matrix-Vector Multiplication in Oblivious Message Retrieval
by: Bosworth, Grant, et al.
Published: (2025)

"vcd2df" -- Leveraging Data Science Insights for Hardware Security Research
by: Deutschbein, Calvin, et al.
Published: (2025)

LLMs and the Future of Chip Design: Unveiling Security Risks and Building Trust
by: Wang, Zeng, et al.
Published: (2024)

DRsam: Detection of Fault-Based Microarchitectural Side-Channel Attacks in RISC-V Using Statistical Preprocessing and Association Rule Mining
by: Hassan, Muhammad, et al.
Published: (2025)

Security Properties for Open-Source Hardware Designs
by: Rogers, Jayden, et al.
Published: (2024)

The Quest to Build Trust Earlier in Digital Design
by: Tan, Benjamin
Published: (2024)

Secure Multi-Path Routing with All-or-Nothing Transform for Network-on-Chip Architectures
by: Weerasena, Hansika, et al.
Published: (2026)

Cassandra: Efficient Enforcement of Sequential Execution for Cryptographic Programs (Extended Version)
by: Hajiabadi, Ali, et al.
Published: (2024)