Benchmarking and Validation of Sub-mW 30GHz VG-LNAs in 22nm FDSOI CMOS for 5G/6G Phased-Array Receivers
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arXiv
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| Format: | Preprint |
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2024
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| _version_ | 1866929498142801920 |
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| author | Zito, Domenico Spasaro, Michele |
| author_facet | Zito, Domenico Spasaro, Michele |
| contents | Next-generation (5G/6G) wireless systems demand low-power mm-wave phased-array ICs. Variable-gain LNAs (VGLNAs) are key building blocks enabling hardware complexity reduction, performance enhancement and functionality extension. This paper reports a performance benchmarking of two low-power 30GHz VG-LNAs for phased-array ICs, which provide a 7.5dB gain control for 18dB Taylor taper in a 30GHz 8x8 antenna array, for a comprehensive validation of the new class of VGLNAs and its design methodology. In particular, this paper reports a second and implementation (VG-LNA2) with a reduced number (four) of gain-control back-gate voltages and super-low-Vt MOSFETs, with respect to the previous first implementation (VG-LNA1) with six gain-control back-gate voltages and regular- Vt MOSFETs, both in the same 22nm FDSOI CMOS technology. The results show that VG-LNA2 exhibits performance comparable to those of VG-LNA1, with a slightly lower power consumption. Overall, the performance benchmarking shows that the design methodology adopted for the new class of VG-LNAs leads to record low-power consumption and small form factor solutions reaching the targeted performances, regardless of the arrangements of the back-gate voltages for gain control and transistor sets, resulting in a comprehensive validation of the innovative design features and effective design methodology. |
| format | Preprint |
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arxiv_https___arxiv_org_abs_2409_07069 |
| institution | arXiv |
| publishDate | 2024 |
| record_format | arxiv |
| spellingShingle | Benchmarking and Validation of Sub-mW 30GHz VG-LNAs in 22nm FDSOI CMOS for 5G/6G Phased-Array Receivers Zito, Domenico Spasaro, Michele Signal Processing Next-generation (5G/6G) wireless systems demand low-power mm-wave phased-array ICs. Variable-gain LNAs (VGLNAs) are key building blocks enabling hardware complexity reduction, performance enhancement and functionality extension. This paper reports a performance benchmarking of two low-power 30GHz VG-LNAs for phased-array ICs, which provide a 7.5dB gain control for 18dB Taylor taper in a 30GHz 8x8 antenna array, for a comprehensive validation of the new class of VGLNAs and its design methodology. In particular, this paper reports a second and implementation (VG-LNA2) with a reduced number (four) of gain-control back-gate voltages and super-low-Vt MOSFETs, with respect to the previous first implementation (VG-LNA1) with six gain-control back-gate voltages and regular- Vt MOSFETs, both in the same 22nm FDSOI CMOS technology. The results show that VG-LNA2 exhibits performance comparable to those of VG-LNA1, with a slightly lower power consumption. Overall, the performance benchmarking shows that the design methodology adopted for the new class of VG-LNAs leads to record low-power consumption and small form factor solutions reaching the targeted performances, regardless of the arrangements of the back-gate voltages for gain control and transistor sets, resulting in a comprehensive validation of the innovative design features and effective design methodology. |
| title | Benchmarking and Validation of Sub-mW 30GHz VG-LNAs in 22nm FDSOI CMOS for 5G/6G Phased-Array Receivers |
| topic | Signal Processing |
| url | https://arxiv.org/abs/2409.07069 |