Micro-orchestration of RAN functions accelerated in FPGA SoC devices
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arXiv
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| Hauptverfasser: | , , , , |
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| Format: | Preprint |
| Veröffentlicht: |
2024
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| _version_ | 1866910608180379648 |
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| author | Bartzoudis, Nikolaos Fernández, José Rubio López-Bueno, David Kibalya, Godfrey Antonopoulos, Angelos |
| author_facet | Bartzoudis, Nikolaos Fernández, José Rubio López-Bueno, David Kibalya, Godfrey Antonopoulos, Angelos |
| contents | This work provides a vision on how to tackle the underutilization of compute resources in FPGA SoC devices used across 5G and edge computing infrastructures. A first step towards this end is the implementation of a resource management layer able to migrate and scale functions in such devices, based on context events. This layer sets the basis to design a hierarchical data-driven micro-orchestrator in charge of providing the lifecycle management of functions in FPGA SoC devices. In the O-RAN context, the micro-orchestrator is foreseen to take the form of an xApp/rApp tandem trained with RAN traffic and context data. |
| format | Preprint |
| id |
arxiv_https___arxiv_org_abs_2409_11362 |
| institution | arXiv |
| publishDate | 2024 |
| record_format | arxiv |
| spellingShingle | Micro-orchestration of RAN functions accelerated in FPGA SoC devices Bartzoudis, Nikolaos Fernández, José Rubio López-Bueno, David Kibalya, Godfrey Antonopoulos, Angelos Networking and Internet Architecture This work provides a vision on how to tackle the underutilization of compute resources in FPGA SoC devices used across 5G and edge computing infrastructures. A first step towards this end is the implementation of a resource management layer able to migrate and scale functions in such devices, based on context events. This layer sets the basis to design a hierarchical data-driven micro-orchestrator in charge of providing the lifecycle management of functions in FPGA SoC devices. In the O-RAN context, the micro-orchestrator is foreseen to take the form of an xApp/rApp tandem trained with RAN traffic and context data. |
| title | Micro-orchestration of RAN functions accelerated in FPGA SoC devices |
| topic | Networking and Internet Architecture |
| url | https://arxiv.org/abs/2409.11362 |