Hardware/Algorithm Co-design for Real-Time I/O Control with Improved Timing Accuracy and Robustness
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arXiv
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| Auteurs principaux: | , , , , , |
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| Format: | Preprint |
| Publié: |
2024
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| _version_ | 1866913513158475776 |
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| author | Jiang, Zhe Zhao, Shuai Wei, Ran Si, Xin Chen, Gang Guan, Nan |
| author_facet | Jiang, Zhe Zhao, Shuai Wei, Ran Si, Xin Chen, Gang Guan, Nan |
| contents | In safety-critical systems, timing accuracy is the key to achieving precise I/O control. To meet such strict timing requirements, dedicated hardware assistance has recently been investigated and developed. However, these solutions are often fragile, due to unforeseen timing defects. In this paper, we propose a robust and timing-accurate I/O co-processor, which manages I/O tasks using Execution Time Servers (ETSs) and a two-level scheduler. The ETSs limit the impact of timing defects between tasks, and the scheduler prioritises ETSs based on their importance, offering a robust and configurable scheduling infrastructure. Based on the hardware design, we present an ETS-based timing-accurate I/O schedule, with the ETS parameters configured to further enhance robustness against timing defects. Experiments show the proposed I/O control method outperforms the state-of-the-art method in terms of timing accuracy and robustness without introducing significant overhead. |
| format | Preprint |
| id |
arxiv_https___arxiv_org_abs_2409_14779 |
| institution | arXiv |
| publishDate | 2024 |
| record_format | arxiv |
| spellingShingle | Hardware/Algorithm Co-design for Real-Time I/O Control with Improved Timing Accuracy and Robustness Jiang, Zhe Zhao, Shuai Wei, Ran Si, Xin Chen, Gang Guan, Nan Hardware Architecture C.3; D.4.7 In safety-critical systems, timing accuracy is the key to achieving precise I/O control. To meet such strict timing requirements, dedicated hardware assistance has recently been investigated and developed. However, these solutions are often fragile, due to unforeseen timing defects. In this paper, we propose a robust and timing-accurate I/O co-processor, which manages I/O tasks using Execution Time Servers (ETSs) and a two-level scheduler. The ETSs limit the impact of timing defects between tasks, and the scheduler prioritises ETSs based on their importance, offering a robust and configurable scheduling infrastructure. Based on the hardware design, we present an ETS-based timing-accurate I/O schedule, with the ETS parameters configured to further enhance robustness against timing defects. Experiments show the proposed I/O control method outperforms the state-of-the-art method in terms of timing accuracy and robustness without introducing significant overhead. |
| title | Hardware/Algorithm Co-design for Real-Time I/O Control with Improved Timing Accuracy and Robustness |
| topic | Hardware Architecture C.3; D.4.7 |
| url | https://arxiv.org/abs/2409.14779 |