MESC: Re-thinking Algorithmic Priority and/or Criticality Inversions for Heterogeneous MCSs
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arXiv
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| Autori principali: | , , , , , , |
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| Natura: | Preprint |
| Pubblicazione: |
2024
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| _version_ | 1866917782753378304 |
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| author | Guan, Jiapeng Wei, Ran You, Dean Wang, Yingquan Yang, Ruizhe Wang, Hui Jiang, Zhe |
| author_facet | Guan, Jiapeng Wei, Ran You, Dean Wang, Yingquan Yang, Ruizhe Wang, Hui Jiang, Zhe |
| contents | Modern Mixed-Criticality Systems (MCSs) rely on hardware heterogeneity to satisfy ever-increasing computational demands. However, most of the heterogeneous co-processors are designed to achieve high throughput, with their micro-architectures executing the workloads in a streaming manner. This streaming execution is often non-preemptive or limited-preemptive, preventing tasks' prioritisation based on their importance and resulting in frequent occurrences of algorithmic priority and/or criticality inversions. Such problems present a significant barrier to guaranteeing the systems' real-time predictability, especially when co-processors dominate the execution of the workloads (e.g., DNNs and transformers).
In contrast to existing works that typically enable coarse-grained context switch by splitting the workloads/algorithms, we demonstrate a method that provides fine-grained context switch on a widely used open-source DNN accelerator by enabling instruction-level preemption without any workloads/algorithms modifications. As a systematic solution, we build a real system, i.e., Make Each Switch Count (MESC), from the SoC and ISA to the OS kernel. A theoretical model and analysis are also provided for timing guarantees. Experimental results reveal that, compared to conventional MCSs using non-preemptive DNN accelerators, MESC achieved a 250x and 300x speedup in resolving algorithmic priority and criticality inversions, with less than 5\% overhead. To our knowledge, this is the first work investigating algorithmic priority and criticality inversions for MCSs at the instruction level. |
| format | Preprint |
| id |
arxiv_https___arxiv_org_abs_2409_14837 |
| institution | arXiv |
| publishDate | 2024 |
| record_format | arxiv |
| spellingShingle | MESC: Re-thinking Algorithmic Priority and/or Criticality Inversions for Heterogeneous MCSs Guan, Jiapeng Wei, Ran You, Dean Wang, Yingquan Yang, Ruizhe Wang, Hui Jiang, Zhe Hardware Architecture C.3; D.4.7 Modern Mixed-Criticality Systems (MCSs) rely on hardware heterogeneity to satisfy ever-increasing computational demands. However, most of the heterogeneous co-processors are designed to achieve high throughput, with their micro-architectures executing the workloads in a streaming manner. This streaming execution is often non-preemptive or limited-preemptive, preventing tasks' prioritisation based on their importance and resulting in frequent occurrences of algorithmic priority and/or criticality inversions. Such problems present a significant barrier to guaranteeing the systems' real-time predictability, especially when co-processors dominate the execution of the workloads (e.g., DNNs and transformers). In contrast to existing works that typically enable coarse-grained context switch by splitting the workloads/algorithms, we demonstrate a method that provides fine-grained context switch on a widely used open-source DNN accelerator by enabling instruction-level preemption without any workloads/algorithms modifications. As a systematic solution, we build a real system, i.e., Make Each Switch Count (MESC), from the SoC and ISA to the OS kernel. A theoretical model and analysis are also provided for timing guarantees. Experimental results reveal that, compared to conventional MCSs using non-preemptive DNN accelerators, MESC achieved a 250x and 300x speedup in resolving algorithmic priority and criticality inversions, with less than 5\% overhead. To our knowledge, this is the first work investigating algorithmic priority and criticality inversions for MCSs at the instruction level. |
| title | MESC: Re-thinking Algorithmic Priority and/or Criticality Inversions for Heterogeneous MCSs |
| topic | Hardware Architecture C.3; D.4.7 |
| url | https://arxiv.org/abs/2409.14837 |