MESC: Re-thinking Algorithmic Priority and/or Criticality Inversions for Heterogeneous MCSs
Fuente:
arXiv
Guardado en:
| Autores principales: | Guan, Jiapeng, Wei, Ran, You, Dean, Wang, Yingquan, Yang, Ruizhe, Wang, Hui, Jiang, Zhe |
|---|---|
| Formato: | Preprint |
| Publicado: |
2024
|
| Materias: | |
| Acceso en línea: | |
| Etiquetas: |
Agregar Etiqueta
Sin Etiquetas, Sea el primero en etiquetar este registro!
|
Ejemplares similares
Hardware/Algorithm Co-design for Real-Time I/O Control with Improved Timing Accuracy and Robustness
por: Jiang, Zhe, et al.
Publicado: (2024)
por: Jiang, Zhe, et al.
Publicado: (2024)
Strix: Re-thinking NPU Reliability from a System Perspective
por: Guan, Jiapeng, et al.
Publicado: (2026)
por: Guan, Jiapeng, et al.
Publicado: (2026)
MEEK: Re-thinking Heterogeneous Parallel Error Detection Architecture for Real-World OoO Superscalar Processors
por: Jiang, Zhe, et al.
Publicado: (2025)
por: Jiang, Zhe, et al.
Publicado: (2025)
Arm DynamIQ Shared Unit and Real-Time: An Empirical Evaluation
por: Pradhan, Ashutosh, et al.
Publicado: (2025)
por: Pradhan, Ashutosh, et al.
Publicado: (2025)
MERE: Hardware-Software Co-Design for Masking Cache Miss Latency in Embedded Processors
por: You, Dean, et al.
Publicado: (2025)
por: You, Dean, et al.
Publicado: (2025)
From Characterization to Microarchitecture: Designing an Elegant and Reliable BFP-Based NPU
por: Zhang, Jie, et al.
Publicado: (2026)
por: Zhang, Jie, et al.
Publicado: (2026)
MEIC: Re-thinking RTL Debug Automation using LLMs
por: Xu, Ke, et al.
Publicado: (2024)
por: Xu, Ke, et al.
Publicado: (2024)
ISAAC: Intelligent, Scalable, Agile, and Accelerated CPU Verification via LLM-aided FPGA Parallelism
por: Sun, Jialin, et al.
Publicado: (2025)
por: Sun, Jialin, et al.
Publicado: (2025)
NVR: Vector Runahead on NPUs for Sparse Memory Access
por: Wang, Hui, et al.
Publicado: (2025)
por: Wang, Hui, et al.
Publicado: (2025)
TOM: A Ternary Read-only Memory Accelerator for LLM-powered Edge Intelligence
por: Guan, Hongyi, et al.
Publicado: (2026)
por: Guan, Hongyi, et al.
Publicado: (2026)
Re-thinking Memory-Bound Limitations in CGRAs
por: Liu, Xiangfeng, et al.
Publicado: (2025)
por: Liu, Xiangfeng, et al.
Publicado: (2025)
ReChisel: Effective Automatic Chisel Code Generation by LLM with Reflection
por: Niu, Juxin, et al.
Publicado: (2025)
por: Niu, Juxin, et al.
Publicado: (2025)
Critical Path Aware Timing-Driven Global Placement for Large-Scale Heterogeneous FPGAs
por: Jiang, He, et al.
Publicado: (2025)
por: Jiang, He, et al.
Publicado: (2025)
FlexStep: Enabling Flexible Error Detection in Multi/Many-core Real-time Systems
por: Wang, Tinglue, et al.
Publicado: (2025)
por: Wang, Tinglue, et al.
Publicado: (2025)
Accelerating OTA Circuit Design: Transistor Sizing Based on a Transformer Model and Precomputed Lookup Tables
por: Ghosh, Subhadip, et al.
Publicado: (2025)
por: Ghosh, Subhadip, et al.
Publicado: (2025)
MANTIS: A Mixed-Signal Near-Sensor Convolutional Imager SoC Using Charge-Domain 4b-Weighted 5-to-84-TOPS/W MAC Operations for Feature Extraction and Region-of-Interest Detection
por: Lefebvre, Martin, et al.
Publicado: (2024)
por: Lefebvre, Martin, et al.
Publicado: (2024)
NeuroPDE: A Neuromorphic PDE Solver Based on Spintronic and Ferroelectric Devices
por: Fu, Siqing, et al.
Publicado: (2025)
por: Fu, Siqing, et al.
Publicado: (2025)
A 2.5-nA Area-Efficient Temperature-Independent 176-/82-ppm/°C CMOS-Only Current Reference in 0.11-$μ$m Bulk and 22-nm FD-SOI
por: Lefebvre, Martin, et al.
Publicado: (2024)
por: Lefebvre, Martin, et al.
Publicado: (2024)
A nA-Range Area-Efficient Sub-100-ppm/°C Peaking Current Reference Using Forward Body Biasing in 0.11-$μ$m Bulk and 22-nm FD-SOI
por: Lefebvre, Martin, et al.
Publicado: (2024)
por: Lefebvre, Martin, et al.
Publicado: (2024)
A 1.1- / 0.9-nA Temperature-Independent 213- / 565-ppm/$^\circ$C Self-Biased CMOS-Only Current Reference in 65-nm Bulk and 22-nm FDSOI
por: Lefebvre, Martin, et al.
Publicado: (2023)
por: Lefebvre, Martin, et al.
Publicado: (2023)
A Paradigm for Generalized Multi-Level Priority Encoders
por: Phillips, Maxwell, et al.
Publicado: (2026)
por: Phillips, Maxwell, et al.
Publicado: (2026)
AXI-REALM: Safe, Modular and Lightweight Traffic Monitoring and Regulation for Heterogeneous Mixed-Criticality Systems
por: Benz, Thomas, et al.
Publicado: (2025)
por: Benz, Thomas, et al.
Publicado: (2025)
BBAL: A Bidirectional Block Floating Point-Based Quantisation Accelerator for Large Language Models
por: Han, Xiaomeng, et al.
Publicado: (2025)
por: Han, Xiaomeng, et al.
Publicado: (2025)
Large Language Model for Verilog Generation with Code-Structure-Guided Reinforcement Learning
por: Wang, Ning, et al.
Publicado: (2024)
por: Wang, Ning, et al.
Publicado: (2024)
Insights from Rights and Wrongs: A Large Language Model for Solving Assertion Failures in RTL Design
por: Zhou, Jie, et al.
Publicado: (2025)
por: Zhou, Jie, et al.
Publicado: (2025)
Designing Reconfigurable Interconnection Network of Heterogeneous Chiplets Using Kalman Filter
por: Biglari, Siamak, et al.
Publicado: (2024)
por: Biglari, Siamak, et al.
Publicado: (2024)
Development of an Energy-Efficient and Real-Time Data Movement Strategy for Next-Generation Heterogeneous Mixed-Criticality Systems
por: Benz, Thomas
Publicado: (2026)
por: Benz, Thomas
Publicado: (2026)
Algorithm-hardware co-design for Energy-Efficient A/D conversion in ReRAM-based accelerators
por: Zhang, Chenguang, et al.
Publicado: (2024)
por: Zhang, Chenguang, et al.
Publicado: (2024)
A Hardware-Based Multi-Stage Dynamic Power Management Architecture for Autonomous Low-Light Operation
por: Kouzinopoulos, Charalampos S., et al.
Publicado: (2026)
por: Kouzinopoulos, Charalampos S., et al.
Publicado: (2026)
An All-digital 8.6-nJ/Frame 65-nm Tsetlin Machine Image Classification Accelerator
por: Tunheim, Svein Anders, et al.
Publicado: (2025)
por: Tunheim, Svein Anders, et al.
Publicado: (2025)
VerilogMonkey: Exploring Parallel Scaling for Automated Verilog Code Generation with LLMs
por: Niu, Juxin, et al.
Publicado: (2025)
por: Niu, Juxin, et al.
Publicado: (2025)
HPIM: Heterogeneous Processing-In-Memory-based Accelerator for Large Language Models Inference
por: Duan, Cenlin, et al.
Publicado: (2025)
por: Duan, Cenlin, et al.
Publicado: (2025)
Insights from Verification: Training a Verilog Generation LLM with Reinforcement Learning with Testbench Feedback
por: Wang, Ning, et al.
Publicado: (2025)
por: Wang, Ning, et al.
Publicado: (2025)
Location is Key: Leveraging Large Language Model for Functional Bug Localization in Verilog
por: Yao, Bingkun, et al.
Publicado: (2024)
por: Yao, Bingkun, et al.
Publicado: (2024)
UVLLM: An Automated Universal RTL Verification Framework using LLMs
por: Hu, Yuchen, et al.
Publicado: (2024)
por: Hu, Yuchen, et al.
Publicado: (2024)
Analytical Heterogeneous Die-to-Die 3D Placement with Macros
por: Zhao, Yuxuan, et al.
Publicado: (2024)
por: Zhao, Yuxuan, et al.
Publicado: (2024)
ReDas: A Lightweight Architecture for Supporting Fine-Grained Reshaping and Multiple Dataflows on Systolic Array
por: Han, Meng, et al.
Publicado: (2023)
por: Han, Meng, et al.
Publicado: (2023)
Adaptive Cache Pollution Control for Large Language Model Inference Workloads Using Temporal CNN-Based Prediction and Priority-Aware Replacement
por: Liu, Songze, et al.
Publicado: (2025)
por: Liu, Songze, et al.
Publicado: (2025)
Mixed Structural Choice Operator: Enhancing Technology Mapping with Heterogeneous Representations
por: Hu, Zhang, et al.
Publicado: (2025)
por: Hu, Zhang, et al.
Publicado: (2025)
CIM-Tuner: Balancing the Compute and Storage Capacity of SRAM-CIM Accelerator via Hardware-mapping Co-exploration
por: Chen, Jinwu, et al.
Publicado: (2026)
por: Chen, Jinwu, et al.
Publicado: (2026)
Ejemplares similares
-
Hardware/Algorithm Co-design for Real-Time I/O Control with Improved Timing Accuracy and Robustness
por: Jiang, Zhe, et al.
Publicado: (2024) -
Strix: Re-thinking NPU Reliability from a System Perspective
por: Guan, Jiapeng, et al.
Publicado: (2026) -
MEEK: Re-thinking Heterogeneous Parallel Error Detection Architecture for Real-World OoO Superscalar Processors
por: Jiang, Zhe, et al.
Publicado: (2025) -
Arm DynamIQ Shared Unit and Real-Time: An Empirical Evaluation
por: Pradhan, Ashutosh, et al.
Publicado: (2025) -
MERE: Hardware-Software Co-Design for Masking Cache Miss Latency in Embedded Processors
por: You, Dean, et al.
Publicado: (2025)