Cover Image

Location is Key: Leveraging Large Language Model for Functional Bug Localization in Verilog

Fuente: arXiv

Saved in:

Bibliographic Details
Main Authors:	Yao, Bingkun, Wang, Ning, Zhou, Jie, Wang, Xi, Gao, Hong, Jiang, Zhe, Guan, Nan
Format:	Preprint
Published:	2024
Subjects:	Hardware Architecture Artificial Intelligence
Online Access:	Acceder al recurso
Tags:	Add Tag No Tags, Be the first to tag this record!

Similar Items

Large Language Model for Verilog Generation with Code-Structure-Guided Reinforcement Learning
by: Wang, Ning, et al.
Published: (2024)

Insights from Verification: Training a Verilog Generation LLM with Reinforcement Learning with Testbench Feedback
by: Wang, Ning, et al.
Published: (2025)

VeriDebug: A Unified LLM for Verilog Debugging via Contrastive Embedding and Guided Correction
by: Wang, Ning, et al.
Published: (2025)

Insights from Rights and Wrongs: A Large Language Model for Solving Assertion Failures in RTL Design
by: Zhou, Jie, et al.
Published: (2025)

VerilogMonkey: Exploring Parallel Scaling for Automated Verilog Code Generation with LLMs
by: Niu, Juxin, et al.
Published: (2025)

LintLLM: An Open-Source Verilog Linting Framework Based on Large Language Models
by: Fang, Zhigang, et al.
Published: (2025)

EvoVerilog: Large Langugage Model Assisted Evolution of Verilog Code
by: Guo, Ping, et al.
Published: (2025)

AutoVeriFix: Automatically Correcting Errors and Enhancing Functional Correctness in LLM-Generated Verilog Code
by: Tan, Yan, et al.
Published: (2025)

UVLLM: An Automated Universal RTL Verification Framework using LLMs
by: Hu, Yuchen, et al.
Published: (2024)

BBAL: A Bidirectional Block Floating Point-Based Quantisation Accelerator for Large Language Models
by: Han, Xiaomeng, et al.
Published: (2025)

VerilogCL: A Contrastive Learning Framework for Robust LLM-Based Verilog Generation
by: Tan, Yan, et al.
Published: (2026)

LLM-VeriPPA: Power, Performance, and Area Optimization aware Verilog Code Generation with Large Language Models
by: Thorat, Kiran, et al.
Published: (2025)

Large Language Model for Verilog Code Generation: Literature Review and the Road Ahead
by: Yang, Guang, et al.
Published: (2025)

ReChisel: Effective Automatic Chisel Code Generation by LLM with Reflection
by: Niu, Juxin, et al.
Published: (2025)

From Characterization to Microarchitecture: Designing an Elegant and Reliable BFP-Based NPU
by: Zhang, Jie, et al.
Published: (2026)

VRank: Enhancing Verilog Code Generation from Large Language Models via Self-Consistency
by: Zhao, Zhuorui, et al.
Published: (2025)

Revisiting VerilogEval: A Year of Improvements in Large-Language Models for Hardware Code Generation
by: Pinckney, Nathaniel, et al.
Published: (2024)

SpeedLLM: An FPGA Co-design of Large Language Model Inference Accelerator
by: Wang, Peipei, et al.
Published: (2025)

Natural Language to Verilog: Design of a Recurrent Spiking Neural Network using Large Language Models and ChatGPT
by: Vitolo, Paola, et al.
Published: (2024)

UVMarvel: an Automated LLM-aided UVM Machine for Subsystem-level RTL Verification
by: Ye, Junhao, et al.
Published: (2026)

AutoVCoder: A Systematic Framework for Automated Verilog Code Generation using LLMs
by: Gao, Mingzhe, et al.
Published: (2024)

Comprehensive Verilog Design Problems: A Next-Generation Benchmark Dataset for Evaluating Large Language Models and Agents on RTL Design and Verification
by: Pinckney, Nathaniel, et al.
Published: (2025)

Pecker: Bug Localization Framework for Sequential Designs via Causal Chain Reconstruction
by: Tang, Jiaping, et al.
Published: (2026)

Python-based DSL for generating Verilog model of Synchronous Digital Circuits
by: Datar, Mandar, et al.
Published: (2024)

Strix: Re-thinking NPU Reliability from a System Perspective
by: Guan, Jiapeng, et al.
Published: (2026)

VeriBug: An Attention-based Framework for Bug-Localization in Hardware Designs
by: Stracquadanio, Giuseppe, et al.
Published: (2024)

From Concept to Practice: an Automated LLM-aided UVM Machine for RTL Verification
by: Ye, Junhao, et al.
Published: (2025)

ISAAC: Intelligent, Scalable, Agile, and Accelerated CPU Verification via LLM-aided FPGA Parallelism
by: Sun, Jialin, et al.
Published: (2025)

HDLFORGE: A Two-Stage Multi-Agent Framework for Efficient Verilog Code Generation with Adaptive Model Escalation
by: Abdollahi, Armin, et al.
Published: (2026)

ReasoningV: Efficient Verilog Code Generation with Adaptive Hybrid Reasoning Model
by: Qin, Haiyan, et al.
Published: (2025)

Wit-HW: Bug Localization in Hardware Design Code via Witness Test Case Generation
by: Ma, Ruiyang, et al.
Published: (2025)

Veritas: Deterministic Verilog Code Synthesis from LLM-Generated Conjunctive Normal Form
by: Roy, Prithwish Basu, et al.
Published: (2025)

SynFuzz: Leveraging Fuzzing of Netlist to Detect Synthesis Bugs
by: Saravanan, Raghul, et al.
Published: (2025)

Natural language is not enough: Benchmarking multi-modal generative AI for Verilog generation
by: Chang, Kaiyan, et al.
Published: (2024)

VFocus: Better Verilog Generation from Large Language Model via Focused Reasoning
by: Zhao, Zhuorui, et al.
Published: (2025)

Annotating Slack Directly on Your Verilog: Fine-Grained RTL Timing Evaluation for Early Optimization
by: Fang, Wenji, et al.
Published: (2024)

HPIM: Heterogeneous Processing-In-Memory-based Accelerator for Large Language Models Inference
by: Duan, Cenlin, et al.
Published: (2025)

ChatSVA: Bridging SVA Generation for Hardware Verification via Task-Specific LLMs
by: Fu, Lik Tung, et al.
Published: (2026)

Theseus: Exploring Efficient Wafer-Scale Chip Design for Large Language Models
by: Zhu, Jingchen, et al.
Published: (2024)

Exploring the Agentic Frontier of Verilog Code Generation
by: Yubeaton, Patrick, et al.
Published: (2026)