Omni 3D: BEOL-Compatible 3D Logic with Omnipresent Power, Signal, and Clock
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| Main Authors: | , , , , , |
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| Format: | Preprint |
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2024
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| _version_ | 1866916410721042432 |
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| author | Choi, Suhyeong Gilardi, Carlo Gutwin, Paul Radway, Robert M. Srimani, Tathagata Mitra, Subhasish |
| author_facet | Choi, Suhyeong Gilardi, Carlo Gutwin, Paul Radway, Robert M. Srimani, Tathagata Mitra, Subhasish |
| contents | This paper presents Omni 3D - a 3D-stacked device architecture that is naturally enabled by back-end-of-line (BEOL)-compatible transistors. Omni 3D arbitrarily interleaves metal layers for both signal/power with FETs in 3D (i.e., nFETs and pFETs are stacked in 3D). Thus, signal/power routing layers have fine-grained, all-sided access to the FET active regions maximizing 3D standard cell design flexibility. This is in sharp contrast to approaches such as back-side power delivery networks (BSPDNs), complementary FETs (CFETs), and stacked FETs. Importantly, the routing flexibility of Omni 3D is enabled by double-side routing and an interleaved metal (IM) layer for inter- and intra-cell routing, respectively. In this work, we explore Omni 3D variants (e.g., both with and without the IM layer) and optimize these variants using a virtual-source BEOL-FET compact model. We establish a physical design flow that efficiently utilizes the double-side routing in Omni 3D and perform a thorough design-technology-co-optimization (DTCO) of Omni 3D device architecture on several design points. From our design flow, we project 2.0x improvement in the energy-delay product and 1.5x reduction in area compared to the state-of-the-art CFETs with BSPDNs. |
| format | Preprint |
| id |
arxiv_https___arxiv_org_abs_2409_16608 |
| institution | arXiv |
| publishDate | 2024 |
| record_format | arxiv |
| spellingShingle | Omni 3D: BEOL-Compatible 3D Logic with Omnipresent Power, Signal, and Clock Choi, Suhyeong Gilardi, Carlo Gutwin, Paul Radway, Robert M. Srimani, Tathagata Mitra, Subhasish Emerging Technologies Hardware Architecture This paper presents Omni 3D - a 3D-stacked device architecture that is naturally enabled by back-end-of-line (BEOL)-compatible transistors. Omni 3D arbitrarily interleaves metal layers for both signal/power with FETs in 3D (i.e., nFETs and pFETs are stacked in 3D). Thus, signal/power routing layers have fine-grained, all-sided access to the FET active regions maximizing 3D standard cell design flexibility. This is in sharp contrast to approaches such as back-side power delivery networks (BSPDNs), complementary FETs (CFETs), and stacked FETs. Importantly, the routing flexibility of Omni 3D is enabled by double-side routing and an interleaved metal (IM) layer for inter- and intra-cell routing, respectively. In this work, we explore Omni 3D variants (e.g., both with and without the IM layer) and optimize these variants using a virtual-source BEOL-FET compact model. We establish a physical design flow that efficiently utilizes the double-side routing in Omni 3D and perform a thorough design-technology-co-optimization (DTCO) of Omni 3D device architecture on several design points. From our design flow, we project 2.0x improvement in the energy-delay product and 1.5x reduction in area compared to the state-of-the-art CFETs with BSPDNs. |
| title | Omni 3D: BEOL-Compatible 3D Logic with Omnipresent Power, Signal, and Clock |
| topic | Emerging Technologies Hardware Architecture |
| url | https://arxiv.org/abs/2409.16608 |