Narla, S., Kumar, P., & Naeemi, A. (2024). A 5T-2MTJ STT-assisted Spin Orbit Torque based Ternary Content Addressable Memory for Hardware Accelerators.
Style de citation Chicago (17e éd.)Narla, Siri, Piyush Kumar, et Azad Naeemi. A 5T-2MTJ STT-assisted Spin Orbit Torque Based Ternary Content Addressable Memory for Hardware Accelerators. 2024.
Style de citation MLA (9e éd.)Narla, Siri, et al. A 5T-2MTJ STT-assisted Spin Orbit Torque Based Ternary Content Addressable Memory for Hardware Accelerators. 2024.
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