Co-design of a novel CMOS highly parallel, low-power, multi-chip neural network accelerator

Fuente: arXiv

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Bibliographic Details
Main Authors:	Hokenmaier, W, Jurasek, R, Bowen, E, Granger, R, Odom, D
Format:	Preprint
Published:	2024
Subjects:	Distributed, Parallel, and Cluster Computing Artificial Intelligence Hardware Architecture
Online Access:	Acceder al recurso
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Internet

https://arxiv.org/abs/2409.19389