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| Main Authors: | , , , |
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| Format: | Preprint |
| Published: |
2024
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| Subjects: | |
| Online Access: | https://arxiv.org/abs/2409.20506 |
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| _version_ | 1866917058394980352 |
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| author | Serhiayenka, Pavel Roche, Stephen Carlson, Benjamin Hong, Tae Min |
| author_facet | Serhiayenka, Pavel Roche, Stephen Carlson, Benjamin Hong, Tae Min |
| contents | We present a generic parallel implementation of the decision tree-based machine learning (ML) method in hardware description language (HDL) on field programmable gate arrays (FPGA). A regression problem in high energy physics at the Large Hadron Collider is considered: the estimation of the magnitude of missing transverse momentum using boosted decision trees (BDT). A forest of twenty decision trees each with a maximum depth of ten using eight input variables of 16-bit precision is executed with a latency of less than 10 ns using O(0.1%) resources on Xilinx UltraScale+ VU9P -- approximately ten times faster and five times smaller compared to similar designs using high level synthesis (HLS) -- without the use of digital signal processors (DSP) while eliminating the use of block RAM (BRAM). We also demonstrate a potential application in the estimation of muon momentum for ATLAS RPC at HL-LHC. |
| format | Preprint |
| id |
arxiv_https___arxiv_org_abs_2409_20506 |
| institution | arXiv |
| publishDate | 2024 |
| record_format | arxiv |
| spellingShingle | Nanosecond hardware regression trees in FPGA at the LHC Serhiayenka, Pavel Roche, Stephen Carlson, Benjamin Hong, Tae Min High Energy Physics - Experiment Data Analysis, Statistics and Probability Instrumentation and Detectors We present a generic parallel implementation of the decision tree-based machine learning (ML) method in hardware description language (HDL) on field programmable gate arrays (FPGA). A regression problem in high energy physics at the Large Hadron Collider is considered: the estimation of the magnitude of missing transverse momentum using boosted decision trees (BDT). A forest of twenty decision trees each with a maximum depth of ten using eight input variables of 16-bit precision is executed with a latency of less than 10 ns using O(0.1%) resources on Xilinx UltraScale+ VU9P -- approximately ten times faster and five times smaller compared to similar designs using high level synthesis (HLS) -- without the use of digital signal processors (DSP) while eliminating the use of block RAM (BRAM). We also demonstrate a potential application in the estimation of muon momentum for ATLAS RPC at HL-LHC. |
| title | Nanosecond hardware regression trees in FPGA at the LHC |
| topic | High Energy Physics - Experiment Data Analysis, Statistics and Probability Instrumentation and Detectors |
| url | https://arxiv.org/abs/2409.20506 |