Design and In-training Optimization of Binary Search ADC for Flexible Classifiers
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arXiv
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| Format: | Preprint |
| Publié: |
2024
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| _version_ | 1866916513856880640 |
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| author | Duarte, Paula Carolina Lozano Afentaki, Florentia Zervakis, Georgios Tahoori, Mehdi B. |
| author_facet | Duarte, Paula Carolina Lozano Afentaki, Florentia Zervakis, Georgios Tahoori, Mehdi B. |
| contents | Flexible Electronics (FE) offer distinct advantages, including mechanical flexibility and low process temperatures, enabling extremely low-cost production. To address the demands of applications such as smart sensors and wearables, flexible devices must be small and operate at low supply voltages. Additionally, target applications often require classifiers to operate directly on analog sensory input, necessitating the use of Analog to Digital Converters (ADCs) to process the sensory data. However, ADCs present serious challenges, particularly in terms of high area and power consumption, especially when considering stringent area and energy budget. In this work, we target common classifiers in this domain such as MLPs and SVMs and present a holistic approach to mitigate the elevated overhead of analog to digital interfacing in FE. First, we propose a novel design for Binary Search ADC that reduces area overhead 2X compared with the state-of-the-art Binary design and up to 5.4X compared with Flash ADC. Next, we present an in-training ADC optimization in which we keep the bare-minimum representations required and simplifying ADCs by removing unnecessary components. Our in-training optimization further reduces on average the area in terms of transistor count of the required ADCs by 5X for less than 1% accuracy loss. |
| format | Preprint |
| id |
arxiv_https___arxiv_org_abs_2410_00737 |
| institution | arXiv |
| publishDate | 2024 |
| record_format | arxiv |
| spellingShingle | Design and In-training Optimization of Binary Search ADC for Flexible Classifiers Duarte, Paula Carolina Lozano Afentaki, Florentia Zervakis, Georgios Tahoori, Mehdi B. Hardware Architecture Signal Processing Flexible Electronics (FE) offer distinct advantages, including mechanical flexibility and low process temperatures, enabling extremely low-cost production. To address the demands of applications such as smart sensors and wearables, flexible devices must be small and operate at low supply voltages. Additionally, target applications often require classifiers to operate directly on analog sensory input, necessitating the use of Analog to Digital Converters (ADCs) to process the sensory data. However, ADCs present serious challenges, particularly in terms of high area and power consumption, especially when considering stringent area and energy budget. In this work, we target common classifiers in this domain such as MLPs and SVMs and present a holistic approach to mitigate the elevated overhead of analog to digital interfacing in FE. First, we propose a novel design for Binary Search ADC that reduces area overhead 2X compared with the state-of-the-art Binary design and up to 5.4X compared with Flash ADC. Next, we present an in-training ADC optimization in which we keep the bare-minimum representations required and simplifying ADCs by removing unnecessary components. Our in-training optimization further reduces on average the area in terms of transistor count of the required ADCs by 5X for less than 1% accuracy loss. |
| title | Design and In-training Optimization of Binary Search ADC for Flexible Classifiers |
| topic | Hardware Architecture Signal Processing |
| url | https://arxiv.org/abs/2410.00737 |