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| Main Authors: | , , , , |
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| Format: | Preprint |
| Published: |
2024
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| Subjects: | |
| Online Access: | https://arxiv.org/abs/2410.01442 |
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| _version_ | 1866912055590649856 |
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| author | Allart, Côme Coulon, Jean-Roch Sintzoff, André Potin, Olivier Rigaud, Jean-Baptiste |
| author_facet | Allart, Côme Coulon, Jean-Roch Sintzoff, André Potin, Olivier Rigaud, Jean-Baptiste |
| contents | A performance model of CVA6 RISC-V processor is built to evaluate performance related modifications before implementing them in RTL. Its accuracy is 99.2% on CoreMark. This model is used to evaluate a superscalar feature for CVA6. During design phase, the model helped detecting and fixing performance bugs. The superscalar feature resulted in a CVA6 performance improvement of 40% on CoreMark. |
| format | Preprint |
| id |
arxiv_https___arxiv_org_abs_2410_01442 |
| institution | arXiv |
| publishDate | 2024 |
| record_format | arxiv |
| spellingShingle | Using a Performance Model to Implement a Superscalar CVA6 Allart, Côme Coulon, Jean-Roch Sintzoff, André Potin, Olivier Rigaud, Jean-Baptiste Hardware Architecture A performance model of CVA6 RISC-V processor is built to evaluate performance related modifications before implementing them in RTL. Its accuracy is 99.2% on CoreMark. This model is used to evaluate a superscalar feature for CVA6. During design phase, the model helped detecting and fixing performance bugs. The superscalar feature resulted in a CVA6 performance improvement of 40% on CoreMark. |
| title | Using a Performance Model to Implement a Superscalar CVA6 |
| topic | Hardware Architecture |
| url | https://arxiv.org/abs/2410.01442 |