Intelligent Pixel Detectors: Towards a Radiation Hard ASIC with On-Chip Machine Learning in 28 nm CMOS

Fuente: arXiv
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Hauptverfasser: Badea, Anthony, Bean, Alice, Berry, Doug, Dickinson, Jennet, DiPetrillo, Karri, Fahim, Farah, Gray, Lindsey, Di Guglielmo, Giuseppe, Jiang, David, Kovach-Fuentes, Rachel, Maksimovic, Petar, Mills, Corrinne, Neubauer, Mark S., Parpillon, Benjamin, Shekar, Danush, Swartz, Morris, Syal, Chinar, Tran, Nhan, Yoo, Jieun
Format: Preprint
Veröffentlicht: 2024
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author Badea, Anthony
Bean, Alice
Berry, Doug
Dickinson, Jennet
DiPetrillo, Karri
Fahim, Farah
Gray, Lindsey
Di Guglielmo, Giuseppe
Jiang, David
Kovach-Fuentes, Rachel
Maksimovic, Petar
Mills, Corrinne
Neubauer, Mark S.
Parpillon, Benjamin
Shekar, Danush
Swartz, Morris
Syal, Chinar
Tran, Nhan
Yoo, Jieun
author_facet Badea, Anthony
Bean, Alice
Berry, Doug
Dickinson, Jennet
DiPetrillo, Karri
Fahim, Farah
Gray, Lindsey
Di Guglielmo, Giuseppe
Jiang, David
Kovach-Fuentes, Rachel
Maksimovic, Petar
Mills, Corrinne
Neubauer, Mark S.
Parpillon, Benjamin
Shekar, Danush
Swartz, Morris
Syal, Chinar
Tran, Nhan
Yoo, Jieun
contents Detectors at future high energy colliders will face enormous technical challenges. Disentangling the unprecedented numbers of particles expected in each event will require highly granular silicon pixel detectors with billions of readout channels. With event rates as high as 40 MHz, these detectors will generate petabytes of data per second. To enable discovery within strict bandwidth and latency constraints, future trackers must be capable of fast, power efficient, and radiation hard data-reduction at the source. We are developing a radiation hard readout integrated circuit (ROIC) in 28nm CMOS with on-chip machine learning (ML) for future intelligent pixel detectors. We will show track parameter predictions using a neural network within a single layer of silicon and hardware tests on the first tape-outs produced with TSMC. Preliminary results indicate that reading out featurized clusters from particles above a modest momentum threshold could enable using pixel information at 40 MHz.
format Preprint
id arxiv_https___arxiv_org_abs_2410_02945
institution arXiv
publishDate 2024
record_format arxiv
spellingShingle Intelligent Pixel Detectors: Towards a Radiation Hard ASIC with On-Chip Machine Learning in 28 nm CMOS
Badea, Anthony
Bean, Alice
Berry, Doug
Dickinson, Jennet
DiPetrillo, Karri
Fahim, Farah
Gray, Lindsey
Di Guglielmo, Giuseppe
Jiang, David
Kovach-Fuentes, Rachel
Maksimovic, Petar
Mills, Corrinne
Neubauer, Mark S.
Parpillon, Benjamin
Shekar, Danush
Swartz, Morris
Syal, Chinar
Tran, Nhan
Yoo, Jieun
Instrumentation and Detectors
High Energy Physics - Experiment
Detectors at future high energy colliders will face enormous technical challenges. Disentangling the unprecedented numbers of particles expected in each event will require highly granular silicon pixel detectors with billions of readout channels. With event rates as high as 40 MHz, these detectors will generate petabytes of data per second. To enable discovery within strict bandwidth and latency constraints, future trackers must be capable of fast, power efficient, and radiation hard data-reduction at the source. We are developing a radiation hard readout integrated circuit (ROIC) in 28nm CMOS with on-chip machine learning (ML) for future intelligent pixel detectors. We will show track parameter predictions using a neural network within a single layer of silicon and hardware tests on the first tape-outs produced with TSMC. Preliminary results indicate that reading out featurized clusters from particles above a modest momentum threshold could enable using pixel information at 40 MHz.
title Intelligent Pixel Detectors: Towards a Radiation Hard ASIC with On-Chip Machine Learning in 28 nm CMOS
topic Instrumentation and Detectors
High Energy Physics - Experiment
url https://arxiv.org/abs/2410.02945