Saved in:
| Main Authors: | Kuhne, Mark, Volos, Stavros, Shinde, Shweta |
|---|---|
| Format: | Preprint |
| Published: |
2024
|
| Subjects: | |
| Online Access: | https://arxiv.org/abs/2410.03653 |
| Tags: |
Add Tag
No Tags, Be the first to tag this record!
|
Similar Items
Heckler: Breaking Confidential VMs with Malicious Interrupts
by: Schlüter, Benedict, et al.
Published: (2024)
by: Schlüter, Benedict, et al.
Published: (2024)
Aster: Fixing the Android TEE Ecosystem with Arm CCA
by: Kuhne, Mark, et al.
Published: (2024)
by: Kuhne, Mark, et al.
Published: (2024)
OpenCCA: An Open Framework to Enable Arm CCA Research
by: Bertschi, Andrin, et al.
Published: (2025)
by: Bertschi, Andrin, et al.
Published: (2025)
Enhancing the Security of Rollup Sequencers using Decentrally Attested TEEs
by: Cristiano, Giovanni Maria, et al.
Published: (2025)
by: Cristiano, Giovanni Maria, et al.
Published: (2025)
Devlore: Device Interrupt Protection for Confidential VMs
by: Bertschi, Andrin, et al.
Published: (2024)
by: Bertschi, Andrin, et al.
Published: (2024)
Enter, Exit, Page Fault, Leak: Testing Isolation Boundaries for Microarchitectural Leaks
by: Oleksenko, Oleksii, et al.
Published: (2025)
by: Oleksenko, Oleksii, et al.
Published: (2025)
Fastrack: Fast IO for Secure ML using GPU TEEs
by: Wang, Yongqin, et al.
Published: (2024)
by: Wang, Yongqin, et al.
Published: (2024)
Research Directions for Verifiable Crypto-Physically Secure TEEs
by: Bellemare, Sylvain
Published: (2024)
by: Bellemare, Sylvain
Published: (2024)
The Forking Way: When TEEs Meet Consensus
by: Wilde, Annika, et al.
Published: (2024)
by: Wilde, Annika, et al.
Published: (2024)
CryptRISC: A Secure RISC-V Processor for High-Performance Cryptography with Power Side-Channel Protection
by: Srivastava, Amisha, et al.
Published: (2026)
by: Srivastava, Amisha, et al.
Published: (2026)
SIGY: Breaking Intel SGX Enclaves with Malicious Exceptions & Signals
by: Sridhara, Supraja, et al.
Published: (2024)
by: Sridhara, Supraja, et al.
Published: (2024)
WeSee: Using Malicious #VC Interrupts to Break AMD SEV-SNP
by: Schlüter, Benedict, et al.
Published: (2024)
by: Schlüter, Benedict, et al.
Published: (2024)
Securing Transformer-based AI Execution via Unified TEEs and Crypto-protected Accelerators
by: Xue, Jiaqi, et al.
Published: (2025)
by: Xue, Jiaqi, et al.
Published: (2025)
On Securing the Software Development Lifecycle in IoT RISC-V Trusted Execution Environments
by: Wilde, Annika, et al.
Published: (2026)
by: Wilde, Annika, et al.
Published: (2026)
Narrowing the Gap between TEEs Threat Model and Deployment Strategies
by: Rezabek, Filip, et al.
Published: (2025)
by: Rezabek, Filip, et al.
Published: (2025)
RISecure-PUF: Multipurpose PUF-Driven Security Extensions with Lookaside Buffer in RISC-V
by: Chen, Chenghao, et al.
Published: (2024)
by: Chen, Chenghao, et al.
Published: (2024)
ParTEETor: A System for Partial Deployments of TEEs within Tor
by: King, Rachel, et al.
Published: (2024)
by: King, Rachel, et al.
Published: (2024)
RISC-V Needs Secure 'Wheels': the MCU Initiator-Side Perspective
by: Pinto, Sandro, et al.
Published: (2024)
by: Pinto, Sandro, et al.
Published: (2024)
ALPS: Automated Least-Privilege Enforcement for Securing Serverless Functions
by: Shin, Changhee, et al.
Published: (2026)
by: Shin, Changhee, et al.
Published: (2026)
Preventing Prompt Injection with Type-Directed Privilege Separation
by: Jacob, Dennis, et al.
Published: (2025)
by: Jacob, Dennis, et al.
Published: (2025)
Progent: Securing AI Agents with Privilege Control
by: Shi, Tianneng, et al.
Published: (2025)
by: Shi, Tianneng, et al.
Published: (2025)
CrudiTEE: A Stick-and-Carrot Approach to Building Trustworthy Cryptocurrency Wallets with TEEs
by: Zhou, Lulu, et al.
Published: (2024)
by: Zhou, Lulu, et al.
Published: (2024)
Exposing Hidden Backdoors in NFT Smart Contracts: A Static Security Analysis of Rug Pull Patterns
by: Pathade, Chetan, et al.
Published: (2025)
by: Pathade, Chetan, et al.
Published: (2025)
Rolling in the Shadows: Analyzing the Extraction of MEV Across Layer-2 Rollups
by: Torres, Christof Ferreira, et al.
Published: (2024)
by: Torres, Christof Ferreira, et al.
Published: (2024)
SAILOR: A Scalable and Energy-Efficient Ultra-Lightweight RISC-V for IoT Security
by: Ewert, Christian, et al.
Published: (2026)
by: Ewert, Christian, et al.
Published: (2026)
ACE: Confidential Computing for Embedded RISC-V Systems
by: Ozga, Wojciech, et al.
Published: (2025)
by: Ozga, Wojciech, et al.
Published: (2025)
PermuteV: A Performant Side-channel-Resistant RISC-V Core Securing Edge AI Inference
by: Narkthong, Nuntipat, et al.
Published: (2025)
by: Narkthong, Nuntipat, et al.
Published: (2025)
Physical and Software Based Fault Injection Attacks Against TEEs in Mobile Devices: A Systemisation of Knowledge
by: Joy, Aaron, et al.
Published: (2024)
by: Joy, Aaron, et al.
Published: (2024)
Translating Common Security Assertions Across Processor Designs: A RISC-V Case Study
by: Imtiaz, Sharjeel, et al.
Published: (2025)
by: Imtiaz, Sharjeel, et al.
Published: (2025)
Systematic Assessment of Cache Timing Vulnerabilities on RISC-V Processors
by: Austa, Cédrick, et al.
Published: (2025)
by: Austa, Cédrick, et al.
Published: (2025)
Finding Missing Input Validation in TEEs via LLM-Assisted Symbolic Execution
by: Ma, Chengyan, et al.
Published: (2026)
by: Ma, Chengyan, et al.
Published: (2026)
Crypto-RV: High-Efficiency FPGA-Based RISC-V Cryptographic Co-Processor for IoT Security
by: Pham, Anh Kiet, et al.
Published: (2026)
by: Pham, Anh Kiet, et al.
Published: (2026)
DeTRAP: RISC-V Return Address Protection With Debug Triggers
by: Richter, Isaac, et al.
Published: (2024)
by: Richter, Isaac, et al.
Published: (2024)
Securing Generative AI in Healthcare: A Zero-Trust Architecture Powered by Confidential Computing on Google Cloud
by: Amanna, Adaobi, et al.
Published: (2025)
by: Amanna, Adaobi, et al.
Published: (2025)
Agent Privilege Separation in OpenClaw: A Structural Defense Against Prompt Injection
by: Cheng, Darren, et al.
Published: (2026)
by: Cheng, Darren, et al.
Published: (2026)
Hardware-based stack buffer overflow attack detection on RISC-V architectures
by: Chenet, Cristiano Pegoraro, et al.
Published: (2024)
by: Chenet, Cristiano Pegoraro, et al.
Published: (2024)
Synthesizing Hardware-Software Leakage Contracts for RISC-V Open-Source Processors
by: Mohr, Gideon, et al.
Published: (2024)
by: Mohr, Gideon, et al.
Published: (2024)
Synthesis of Sound and Precise Leakage Contracts for Open-Source RISC-V Processors
by: Wang, Zilong, et al.
Published: (2025)
by: Wang, Zilong, et al.
Published: (2025)
CryptoGen: Secure Transformer Generation with Encrypted KV-Cache Reuse
by: Zhang, Hedong, et al.
Published: (2026)
by: Zhang, Hedong, et al.
Published: (2026)
Ringmaster: How to juggle high-throughput host OS system calls from TrustZone TEEs
by: Habeeb, Richard, et al.
Published: (2026)
by: Habeeb, Richard, et al.
Published: (2026)
Similar Items
-
Heckler: Breaking Confidential VMs with Malicious Interrupts
by: Schlüter, Benedict, et al.
Published: (2024) -
Aster: Fixing the Android TEE Ecosystem with Arm CCA
by: Kuhne, Mark, et al.
Published: (2024) -
OpenCCA: An Open Framework to Enable Arm CCA Research
by: Bertschi, Andrin, et al.
Published: (2025) -
Enhancing the Security of Rollup Sequencers using Decentrally Attested TEEs
by: Cristiano, Giovanni Maria, et al.
Published: (2025) -
Devlore: Device Interrupt Protection for Confidential VMs
by: Bertschi, Andrin, et al.
Published: (2024)