Imagen de Portada

Evaluation of Run-Time Energy Efficiency using Controlled Approximation in a RISC-V Core

Fuente: arXiv

Guardado en:

Detalles Bibliográficos
Autores principales:	Delavari, Arvin, Ghoreishy, Faraz, Shahhoseini, Hadi Shahriar, Mirzakuchaki, Sattar
Formato:	Preprint
Publicado:	2024
Materias:	Hardware Architecture
Acceso en línea:	Acceder al recurso
Etiquetas:	Agregar Etiqueta Sin Etiquetas, Sea el primero en etiquetar este registro!

Ejemplares similares

A Reconfigurable Approximate Computing RISC-V Platform for Fault-Tolerant Applications
por: Delavari, Arvin, et al.
Publicado: (2024)

Dynamic Power Control in a Hardware Neural Network with Error-Configurable MAC Units
por: Ghaderi, Maedeh, et al.
Publicado: (2024)

Optimizing Energy Efficiency in Subthreshold RISC-V Cores
por: Djupdal, Asbjørn, et al.
Publicado: (2025)

Runtime Energy Monitoring for RISC-V Soft-Cores
por: Scionti, Alberto, et al.
Publicado: (2025)

Ramping Up Open-Source RISC-V Cores: Assessing the Energy Efficiency of Superscalar, Out-of-Order Execution
por: Fu, Zexin, et al.
Publicado: (2025)

SentryCore: A RISC-V Co-Processor System for Safe, Real-Time Control Applications
por: Rogenmoser, Michael, et al.
Publicado: (2024)

Using Formal Verification to Evaluate Single Event Upsets in a RISC-V Core
por: Xue, Bing, et al.
Publicado: (2024)

Dual-Issue Execution of Mixed Integer and Floating-Point Workloads on Energy-Efficient In-Order RISC-V Cores
por: Colagrande, Luca, et al.
Publicado: (2025)

MultiVic: A Time-Predictable RISC-V Multi-Core Processor Optimized for Neural Network Inference
por: Kirschner, Maximilian, et al.
Publicado: (2025)

Design, Implementation and Evaluation of the SVNAPOT Extension on a RISC-V Processor
por: Papadopoulos, Nikolaos-Charalampos, et al.
Publicado: (2024)

Decoupled Control Flow and Data Access in RISC-V GPGPUs
por: Sarda, Giuseppe M., et al.
Publicado: (2025)

Spatz: Clustering Compact RISC-V-Based Vector Units to Maximize Computing Efficiency
por: Perotti, Matteo, et al.
Publicado: (2023)

Spatzformer: An Efficient Reconfigurable Dual-Core RISC-V V Cluster for Mixed Scalar-Vector Workloads
por: Perotti, Matteo, et al.
Publicado: (2024)

CVA6S+: A Superscalar RISC-V Core with High-Throughput Memory Architecture
por: Tedeschi, Riccardo, et al.
Publicado: (2025)

RISC-Q: A Generator for Real-Time Quantum Control System-on-Chips Compatible with RISC-V
por: Liu, Junyi, et al.
Publicado: (2025)

Efficient Trace for RISC-V: Design, Evaluation, and Integration in CVA6
por: Laghi, Umberto, et al.
Publicado: (2025)

WebRISC-V: A 64-bit RISC-V Pipeline Simulator for Computer Architecture Classes
por: Giorgi, Roberto, et al.
Publicado: (2025)

Hypervisor Extension for a RISC-V Processor
por: Gauchola, Jaume, et al.
Publicado: (2024)

Late Breaking Results: Boosting Efficient Dual-Issue Execution on Lightweight RISC-V Cores
por: Colagrande, Luca, et al.
Publicado: (2026)

Wildcat: Educational RISC-V Microprocessors
por: Schoeberl, Martin
Publicado: (2025)

ControlPULP: A RISC-V On-Chip Parallel Power Controller for Many-Core HPC Processors with FPGA-Based Hardware-In-The-Loop Power and Thermal Emulation
por: Ottaviano, Alessandro, et al.
Publicado: (2023)

MX: Enhancing RISC-V's Vector ISA for Ultra-Low Overhead, Energy-Efficient Matrix Multiplication
por: Perotti, Matteo, et al.
Publicado: (2024)

Towards Zero-Stall Matrix Multiplication on Energy-Efficient RISC-V Clusters for Machine Learning Acceleration
por: Colagrande, Luca, et al.
Publicado: (2025)

Evaluating IOMMU-Based Shared Virtual Addressing for RISC-V Embedded Heterogeneous SoCs
por: Koenig, Cyril, et al.
Publicado: (2025)

Implementing and Optimizing an Open-Source SD-card Host Controller for RISC-V SoCs
por: Vanoni, Axel, et al.
Publicado: (2026)

Web-Based Simulator of Superscalar RISC-V Processors
por: Jaros, Jiri, et al.
Publicado: (2024)

Support Vector Machines Classification on Bendable RISC-V
por: Vergos, Polykarpos, et al.
Publicado: (2025)

Efficient Implementation of RISC-V Vector Permutation Instructions
por: Titopoulos, Vasileios, et al.
Publicado: (2025)

ARISE: Automating RISC-V Instruction Set Extension
por: Hager-Clukas, Andreas, et al.
Publicado: (2025)

Work-in-Progress: Real-Time Neural Network Inference on a Custom RISC-V Multicore Vector Processor
por: Kirschner, Maximilian, et al.
Publicado: (2024)

Verification and Validation (V&V)-in-the-Loop for RISC-V Design: The Holistic Vision of BZL
por: Ahmed, Sajjad, et al.
Publicado: (2026)

RISC-V processor enhanced with a dynamic micro-decoder unit
por: Pottier, Juliette, et al.
Publicado: (2024)

Branch Prediction in Hardcaml for a RISC-V 32im CPU
por: Saveau, Alex
Publicado: (2023)

RISC-V V Vector Extension (RVV) with reduced number of vector registers
por: Jacobs, Eino, et al.
Publicado: (2024)

A Direct Memory Access Controller (DMAC) for Irregular Data Transfers on RISC-V Linux Systems
por: Benz, Thomas, et al.
Publicado: (2025)

Functional ISS-Driven Verification of Superscalar RISC-V Processors
por: Galimberti, Andrea, et al.
Publicado: (2024)

Floating Point HUB Adder for RISC-V Sargantana Processor
por: Bandera, Gerardo, et al.
Publicado: (2024)

Static Hardware Partitioning on RISC-V -- Shortcomings, Limitations, and Prospects
por: Ramsauer, Ralf, et al.
Publicado: (2022)

ControlPULPlet: A Flexible Real-time Multi-core RISC-V Controller for 2.5D Systems-in-package
por: Ottaviano, Alessandro, et al.
Publicado: (2024)

A Reconfigurable Multiplier Architecture for Error-Resilient Applications in RISC-V Core
por: Jaswal, Pragun, et al.
Publicado: (2026)