Optimized Spatial Architecture Mapping Flow for Transformer Accelerators
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arXiv
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| Main Authors: | Xu, Haocheng, Tahmasebi, Faraz, Qiao, Ye, Tian, Hongzheng, Kwon, Hyoukjun, Huang, Sitao |
|---|---|
| Format: | Preprint |
| Published: |
2024
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| Subjects: | |
| Online Access: | |
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