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| Hauptverfasser: | , , , , , , , |
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| Format: | Preprint |
| Veröffentlicht: |
2024
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| Schlagworte: | |
| Online-Zugang: | https://arxiv.org/abs/2410.07989 |
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| _version_ | 1866916431967289344 |
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| author | Faraone, Gabriele Daghero, Francesco Serianni, Eugenio Licastro, Dario Di Carolo, Nicola Grosso, Michelangelo Franchino, Giovanna Antonella Pagliari, Daniele Jahier |
| author_facet | Faraone, Gabriele Daghero, Francesco Serianni, Eugenio Licastro, Dario Di Carolo, Nicola Grosso, Michelangelo Franchino, Giovanna Antonella Pagliari, Daniele Jahier |
| contents | Analog-on-Top Mixed Signal (AMS) Integrated Circuit (IC) design is a time-consuming process predominantly carried out by hand. Within this flow, usually, some area is reserved by the top-level integrator for the placement of digital blocks. Specific features of the area, such as size and shape, have a relevant impact on the possibility of implementing the digital logic with the required functionality. We present a Machine Learning (ML)-based evaluation methodology for predicting the feasibility of digital implementation using a set of high-level features. This approach aims to avoid time-consuming Place-and-Route trials, enabling rapid feedback between Digital and Analog Back-End designers during top-level placement. |
| format | Preprint |
| id |
arxiv_https___arxiv_org_abs_2410_07989 |
| institution | arXiv |
| publishDate | 2024 |
| record_format | arxiv |
| spellingShingle | Machine Learning-based feasibility estimation of digital blocks in BCD technology Faraone, Gabriele Daghero, Francesco Serianni, Eugenio Licastro, Dario Di Carolo, Nicola Grosso, Michelangelo Franchino, Giovanna Antonella Pagliari, Daniele Jahier Machine Learning Analog-on-Top Mixed Signal (AMS) Integrated Circuit (IC) design is a time-consuming process predominantly carried out by hand. Within this flow, usually, some area is reserved by the top-level integrator for the placement of digital blocks. Specific features of the area, such as size and shape, have a relevant impact on the possibility of implementing the digital logic with the required functionality. We present a Machine Learning (ML)-based evaluation methodology for predicting the feasibility of digital implementation using a set of high-level features. This approach aims to avoid time-consuming Place-and-Route trials, enabling rapid feedback between Digital and Analog Back-End designers during top-level placement. |
| title | Machine Learning-based feasibility estimation of digital blocks in BCD technology |
| topic | Machine Learning |
| url | https://arxiv.org/abs/2410.07989 |