RISC-V V Vector Extension (RVV) with reduced number of vector registers
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arXiv
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| Autori principali: | , , , |
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| Natura: | Preprint |
| Pubblicazione: |
2024
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| _version_ | 1866912068989353984 |
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| author | Jacobs, Eino Utyansky, Dmitry Hassan, Muhammad Roecker, Thomas |
| author_facet | Jacobs, Eino Utyansky, Dmitry Hassan, Muhammad Roecker, Thomas |
| contents | To reduce the area of RISC-V Vector extension (RVV) in small processors, the authors are considering one simple modification: reduce the number of registers in the vector register file. The standard 'V' extension requires 32 vector registers that we propose to reduce to 16 or 8 registers. Other features of RVV are still supported. Reducing the number of vector registers does not generate a completely new programming model: although the resulting core does not have binary code compatibility with standard RVV, compiling for it just requires parameterization of the vector register file size in the compiler. The reduced vector register file allows for still high utilization of vector RVV processor core. Many useful signal processing kernels require few registers, and become efficient at 1:4 chaining ratio. |
| format | Preprint |
| id |
arxiv_https___arxiv_org_abs_2410_08396 |
| institution | arXiv |
| publishDate | 2024 |
| record_format | arxiv |
| spellingShingle | RISC-V V Vector Extension (RVV) with reduced number of vector registers Jacobs, Eino Utyansky, Dmitry Hassan, Muhammad Roecker, Thomas Hardware Architecture To reduce the area of RISC-V Vector extension (RVV) in small processors, the authors are considering one simple modification: reduce the number of registers in the vector register file. The standard 'V' extension requires 32 vector registers that we propose to reduce to 16 or 8 registers. Other features of RVV are still supported. Reducing the number of vector registers does not generate a completely new programming model: although the resulting core does not have binary code compatibility with standard RVV, compiling for it just requires parameterization of the vector register file size in the compiler. The reduced vector register file allows for still high utilization of vector RVV processor core. Many useful signal processing kernels require few registers, and become efficient at 1:4 chaining ratio. |
| title | RISC-V V Vector Extension (RVV) with reduced number of vector registers |
| topic | Hardware Architecture |
| url | https://arxiv.org/abs/2410.08396 |