MENAGE: Mixed-Signal Event-Driven Neuromorphic Accelerator for Edge Applications
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arXiv
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| Hauptverfasser: | , , |
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| Format: | Preprint |
| Veröffentlicht: |
2024
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| _version_ | 1866910645256978432 |
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| author | Abdollahi, Armin Kamal, Mehdi Pedram, Massoud |
| author_facet | Abdollahi, Armin Kamal, Mehdi Pedram, Massoud |
| contents | This paper presents a mixed-signal neuromorphic accelerator architecture designed for accelerating inference with event-based neural network models. This fully CMOS-compatible accelerator utilizes analog computing to emulate synapse and neuron operations. A C2C ladder structure implements synapses, while operational amplifiers (op-amps) are used to realize neuron functions. To enhance hardware resource utilization and power efficiency, we introduce the concept of a virtual neuron, where a single neuron engine emulates a set of model neurons, leveraging the sparsity inherent in event-based neuromorphic systems. Additionally, we propose a memory-based control technique to manage events in each layer, which improves performance while maintaining the flexibility to support various layer types. We also introduce an integer linear programming (ILP)-based mapping approach for efficiently allocating the model onto the proposed accelerator. The accelerator is a general-purpose neuromorphic platform capable of executing linear and convolutional neural models. The effectiveness of the proposed architecture is evaluated using two specially designed neuromorphic accelerators and two event-based datasets. The results show that the proposed architecture achieves 12.1 TOPS/W energy efficiency when accelerating a model trained on CIFAR10-DVS. |
| format | Preprint |
| id |
arxiv_https___arxiv_org_abs_2410_08403 |
| institution | arXiv |
| publishDate | 2024 |
| record_format | arxiv |
| spellingShingle | MENAGE: Mixed-Signal Event-Driven Neuromorphic Accelerator for Edge Applications Abdollahi, Armin Kamal, Mehdi Pedram, Massoud Hardware Architecture This paper presents a mixed-signal neuromorphic accelerator architecture designed for accelerating inference with event-based neural network models. This fully CMOS-compatible accelerator utilizes analog computing to emulate synapse and neuron operations. A C2C ladder structure implements synapses, while operational amplifiers (op-amps) are used to realize neuron functions. To enhance hardware resource utilization and power efficiency, we introduce the concept of a virtual neuron, where a single neuron engine emulates a set of model neurons, leveraging the sparsity inherent in event-based neuromorphic systems. Additionally, we propose a memory-based control technique to manage events in each layer, which improves performance while maintaining the flexibility to support various layer types. We also introduce an integer linear programming (ILP)-based mapping approach for efficiently allocating the model onto the proposed accelerator. The accelerator is a general-purpose neuromorphic platform capable of executing linear and convolutional neural models. The effectiveness of the proposed architecture is evaluated using two specially designed neuromorphic accelerators and two event-based datasets. The results show that the proposed architecture achieves 12.1 TOPS/W energy efficiency when accelerating a model trained on CIFAR10-DVS. |
| title | MENAGE: Mixed-Signal Event-Driven Neuromorphic Accelerator for Edge Applications |
| topic | Hardware Architecture |
| url | https://arxiv.org/abs/2410.08403 |