Energy-efficient SNN Architecture using 3nm FinFET Multiport SRAM-based CIM with Online Learning
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arXiv
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| Main Authors: | , , , , , |
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| Format: | Preprint |
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2024
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| _version_ | 1866929538474180608 |
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| author | Huijbregts, Lucas Hsiao-Hsuan, Liu Detterer, Paul Hamdioui, Said Yousefzadeh, Amirreza Bishnoi, Rajendra |
| author_facet | Huijbregts, Lucas Hsiao-Hsuan, Liu Detterer, Paul Hamdioui, Said Yousefzadeh, Amirreza Bishnoi, Rajendra |
| contents | Current Artificial Intelligence (AI) computation systems face challenges, primarily from the memory-wall issue, limiting overall system-level performance, especially for Edge devices with constrained battery budgets, such as smartphones, wearables, and Internet-of-Things sensor systems. In this paper, we propose a new SRAM-based Compute-In-Memory (CIM) accelerator optimized for Spiking Neural Networks (SNNs) Inference. Our proposed architecture employs a multiport SRAM design with multiple decoupled Read ports to enhance the throughput and Transposable Read-Write ports to facilitate online learning. Furthermore, we develop an Arbiter circuit for efficient data-processing and port allocations during the computation. Results for a 128$\times$128 array in 3nm FinFET technology demonstrate a 3.1$\times$ improvement in speed and a 2.2$\times$ enhancement in energy efficiency with our proposed multiport SRAM design compared to the traditional single-port design. At system-level, a throughput of 44 MInf/s at 607 pJ/Inf and 29mW is achieved. |
| format | Preprint |
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arxiv_https___arxiv_org_abs_2410_09130 |
| institution | arXiv |
| publishDate | 2024 |
| record_format | arxiv |
| spellingShingle | Energy-efficient SNN Architecture using 3nm FinFET Multiport SRAM-based CIM with Online Learning Huijbregts, Lucas Hsiao-Hsuan, Liu Detterer, Paul Hamdioui, Said Yousefzadeh, Amirreza Bishnoi, Rajendra Hardware Architecture Neural and Evolutionary Computing Image and Video Processing Current Artificial Intelligence (AI) computation systems face challenges, primarily from the memory-wall issue, limiting overall system-level performance, especially for Edge devices with constrained battery budgets, such as smartphones, wearables, and Internet-of-Things sensor systems. In this paper, we propose a new SRAM-based Compute-In-Memory (CIM) accelerator optimized for Spiking Neural Networks (SNNs) Inference. Our proposed architecture employs a multiport SRAM design with multiple decoupled Read ports to enhance the throughput and Transposable Read-Write ports to facilitate online learning. Furthermore, we develop an Arbiter circuit for efficient data-processing and port allocations during the computation. Results for a 128$\times$128 array in 3nm FinFET technology demonstrate a 3.1$\times$ improvement in speed and a 2.2$\times$ enhancement in energy efficiency with our proposed multiport SRAM design compared to the traditional single-port design. At system-level, a throughput of 44 MInf/s at 607 pJ/Inf and 29mW is achieved. |
| title | Energy-efficient SNN Architecture using 3nm FinFET Multiport SRAM-based CIM with Online Learning |
| topic | Hardware Architecture Neural and Evolutionary Computing Image and Video Processing |
| url | https://arxiv.org/abs/2410.09130 |