Reducing Data Bottlenecks in Distributed, Heterogeneous Neural Networks

Fuente: arXiv
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Autores principales: Lin, Ruhai, Zhu, Rui-Jie, Eshraghian, Jason K.
Formato: Preprint
Publicado: 2024
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author Lin, Ruhai
Zhu, Rui-Jie
Eshraghian, Jason K.
author_facet Lin, Ruhai
Zhu, Rui-Jie
Eshraghian, Jason K.
contents The rapid advancement of embedded multicore and many-core systems has revolutionized computing, enabling the development of high-performance, energy-efficient solutions for a wide range of applications. As models scale up in size, data movement is increasingly the bottleneck to performance. This movement of data can exist between processor and memory, or between cores and chips. This paper investigates the impact of bottleneck size, in terms of inter-chip data traffic, on the performance of deep learning models in embedded multicore and many-core systems. We conduct a systematic analysis of the relationship between bottleneck size, computational resource utilization, and model accuracy. We apply a hardware-software co-design methodology where data bottlenecks are replaced with extremely narrow layers to reduce the amount of data traffic. In effect, time-multiplexing of signals is replaced by learnable embeddings that reduce the demands on chip IOs. Our experiments on the CIFAR100 dataset demonstrate that the classification accuracy generally decreases as the bottleneck ratio increases, with shallower models experiencing a more significant drop compared to deeper models. Hardware-side evaluation reveals that higher bottleneck ratios lead to substantial reductions in data transfer volume across the layers of the neural network. Through this research, we can determine the trade-off between data transfer volume and model performance, enabling the identification of a balanced point that achieves good performance while minimizing data transfer volume. This characteristic allows for the development of efficient models that are well-suited for resource-constrained environments.
format Preprint
id arxiv_https___arxiv_org_abs_2410_09650
institution arXiv
publishDate 2024
record_format arxiv
spellingShingle Reducing Data Bottlenecks in Distributed, Heterogeneous Neural Networks
Lin, Ruhai
Zhu, Rui-Jie
Eshraghian, Jason K.
Distributed, Parallel, and Cluster Computing
Neural and Evolutionary Computing
The rapid advancement of embedded multicore and many-core systems has revolutionized computing, enabling the development of high-performance, energy-efficient solutions for a wide range of applications. As models scale up in size, data movement is increasingly the bottleneck to performance. This movement of data can exist between processor and memory, or between cores and chips. This paper investigates the impact of bottleneck size, in terms of inter-chip data traffic, on the performance of deep learning models in embedded multicore and many-core systems. We conduct a systematic analysis of the relationship between bottleneck size, computational resource utilization, and model accuracy. We apply a hardware-software co-design methodology where data bottlenecks are replaced with extremely narrow layers to reduce the amount of data traffic. In effect, time-multiplexing of signals is replaced by learnable embeddings that reduce the demands on chip IOs. Our experiments on the CIFAR100 dataset demonstrate that the classification accuracy generally decreases as the bottleneck ratio increases, with shallower models experiencing a more significant drop compared to deeper models. Hardware-side evaluation reveals that higher bottleneck ratios lead to substantial reductions in data transfer volume across the layers of the neural network. Through this research, we can determine the trade-off between data transfer volume and model performance, enabling the identification of a balanced point that achieves good performance while minimizing data transfer volume. This characteristic allows for the development of efficient models that are well-suited for resource-constrained environments.
title Reducing Data Bottlenecks in Distributed, Heterogeneous Neural Networks
topic Distributed, Parallel, and Cluster Computing
Neural and Evolutionary Computing
url https://arxiv.org/abs/2410.09650