Dynamic Power Control in a Hardware Neural Network with Error-Configurable MAC Units
Fuente:
arXiv
Saved in:
| Main Authors: | , , , |
|---|---|
| Format: | Preprint |
| Published: |
2024
|
| Subjects: | |
| Online Access: | |
| Tags: |
Add Tag
No Tags, Be the first to tag this record!
|
| _version_ | 1866917802088071168 |
|---|---|
| author | Ghaderi, Maedeh Delavari, Arvin Ghoreishy, Faraz Mirzakuchaki, Sattar |
| author_facet | Ghaderi, Maedeh Delavari, Arvin Ghoreishy, Faraz Mirzakuchaki, Sattar |
| contents | Multi-Layer Perceptrons (MLP) are powerful tools for representing complex, non-linear relationships, making them essential for diverse machine learning and AI applications. Efficient hardware implementation of MLPs can be achieved through many hardware and architectural design techniques. These networks excel at predictive modeling and classification tasks like image classification, making them a popular choice. Approximate computing techniques are increasingly used to optimize critical path delay, area, power, and overall hardware efficiency in high-performance computing systems through controlled error and related trade-offs. This study proposes a hardware MLP neural network implemented in 45nm CMOS technology, in which MAC units of the neurons incorporate error and power controllable approximate multipliers for classification of the MNIST dataset. The optimized network consists of 10 neurons within the hidden layers, occupying 0.026mm2 of area, with 5.55mW at 100MHz frequency in accurate mode and 4.81mW in lowest accuracy mode. The experiments indicate that the proposed design achieves a maximum rate of 13.33% decrease overall and 24.78% in each neuron's power consumption with only a 0.92% decrease in accuracy in comparison with accurate circuit. |
| format | Preprint |
| id |
arxiv_https___arxiv_org_abs_2410_10545 |
| institution | arXiv |
| publishDate | 2024 |
| record_format | arxiv |
| spellingShingle | Dynamic Power Control in a Hardware Neural Network with Error-Configurable MAC Units Ghaderi, Maedeh Delavari, Arvin Ghoreishy, Faraz Mirzakuchaki, Sattar Hardware Architecture Multi-Layer Perceptrons (MLP) are powerful tools for representing complex, non-linear relationships, making them essential for diverse machine learning and AI applications. Efficient hardware implementation of MLPs can be achieved through many hardware and architectural design techniques. These networks excel at predictive modeling and classification tasks like image classification, making them a popular choice. Approximate computing techniques are increasingly used to optimize critical path delay, area, power, and overall hardware efficiency in high-performance computing systems through controlled error and related trade-offs. This study proposes a hardware MLP neural network implemented in 45nm CMOS technology, in which MAC units of the neurons incorporate error and power controllable approximate multipliers for classification of the MNIST dataset. The optimized network consists of 10 neurons within the hidden layers, occupying 0.026mm2 of area, with 5.55mW at 100MHz frequency in accurate mode and 4.81mW in lowest accuracy mode. The experiments indicate that the proposed design achieves a maximum rate of 13.33% decrease overall and 24.78% in each neuron's power consumption with only a 0.92% decrease in accuracy in comparison with accurate circuit. |
| title | Dynamic Power Control in a Hardware Neural Network with Error-Configurable MAC Units |
| topic | Hardware Architecture |
| url | https://arxiv.org/abs/2410.10545 |