Cover Image

Dynamic Power Control in a Hardware Neural Network with Error-Configurable MAC Units

Fuente: arXiv

Saved in:

Bibliographic Details
Main Authors:	Ghaderi, Maedeh, Delavari, Arvin, Ghoreishy, Faraz, Mirzakuchaki, Sattar
Format:	Preprint
Published:	2024
Subjects:	Hardware Architecture
Online Access:	Acceder al recurso
Tags:	Add Tag No Tags, Be the first to tag this record!

Similar Items

Evaluation of Run-Time Energy Efficiency using Controlled Approximation in a RISC-V Core
by: Delavari, Arvin, et al.
Published: (2024)

A Reconfigurable Approximate Computing RISC-V Platform for Fault-Tolerant Applications
by: Delavari, Arvin, et al.
Published: (2024)

Jack Unit: An Area- and Energy-Efficient Multiply-Accumulate (MAC) Unit Supporting Diverse Data Formats
by: Noh, Seock-Hwan, et al.
Published: (2025)

A Configurable and Efficient Memory Hierarchy for Neural Network Hardware Accelerator
by: Bause, Oliver, et al.
Published: (2024)

Table-Lookup MAC: Scalable Processing of Quantised Neural Networks in FPGA Soft Logic
by: Gerlinghoff, Daniel, et al.
Published: (2024)

GRAU: Generic Reconfigurable Activation Unit Design for Neural Network Hardware Accelerators
by: Liu, Yuhao, et al.
Published: (2026)

ReGate: Enabling Power Gating in Neural Processing Units
by: Xue, Yuqi, et al.
Published: (2025)

XtraMAC: An Efficient MAC Architecture for Mixed-Precision LLM Inference on FPGA
by: Yu, Feng, et al.
Published: (2026)

Taming Performance Variability caused by Client-Side Hardware Configuration
by: Antoniou, Georgia, et al.
Published: (2024)

Look-Up Table based Neural Network Hardware
by: Sen, Ovishake, et al.
Published: (2024)

AutoPDR: Circuit-Aware Solver Configuration Prediction for Hardware Model Checking
by: Hu, Guangyu, et al.
Published: (2026)

ONNX-to-Hardware Design Flow for Adaptive Neural-Network Inference on FPGAs
by: Manca, Federico, et al.
Published: (2024)

FETTA: Flexible and Efficient Hardware Accelerator for Tensorized Neural Network Training
by: Lu, Jinming, et al.
Published: (2025)

Overcoming Quadratic Hardware Scaling for a Fully Connected Digital Oscillatory Neural Network
by: Haverkort, Bram, et al.
Published: (2025)

PULSE: Parametric Hardware Units for Low-power Sparsity-Aware Convolution Engine
by: Aliyev, Ilkin, et al.
Published: (2024)

Marco: Configurable Graph-Based Task Solving and Multi-AI Agents Framework for Hardware Design
by: Ho, Chia-Tung, et al.
Published: (2025)

ControlPULP: A RISC-V On-Chip Parallel Power Controller for Many-Core HPC Processors with FPGA-Based Hardware-In-The-Loop Power and Thermal Emulation
by: Ottaviano, Alessandro, et al.
Published: (2023)

A Power-Efficient Hardware Implementation of L-Mul
by: Chen, Ruiqi, et al.
Published: (2024)

Hardware-Aware Neural Network Compilation with Learned Optimization: A RISC-V Accelerator Approach
by: Ganti, Ravindra, et al.
Published: (2025)

e-GPU: An Open-Source and Configurable RISC-V Graphic Processing Unit for TinyAI Applications
by: Machetti, Simone, et al.
Published: (2025)

BinSparX: Sparsified Binary Neural Networks for Reduced Hardware Non-Idealities in Xbar Arrays
by: Malhotra, Akul, et al.
Published: (2024)

NeuroVM: Dynamic Neuromorphic Hardware Virtualization
by: Isik, Murat, et al.
Published: (2024)

Reusing Softmax Hardware Unit for GELU Computation in Transformers
by: Peltekis, Christodoulos, et al.
Published: (2024)

NeuroAI Temporal Neural Networks (NeuTNNs): Microarchitecture and Design Framework for Specialized Neuromorphic Processing Units
by: Venkatachalam, Shanmuga, et al.
Published: (2026)

Shavette: Low Power Neural Network Acceleration via Algorithm-level Error Detection and Undervolting
by: Rinkinen, Mikael, et al.
Published: (2024)

In-Situ Hardware Error Detection Using Specification-Derived Petri Net Models and Behavior-Derived State Sequences
by: Tanaka, Tomonari, et al.
Published: (2025)

MiniFloat-NN and ExSdotp: An ISA Extension and a Modular Open Hardware Unit for Low-Precision Training on RISC-V cores
by: Bertaccini, Luca, et al.
Published: (2022)

UFO-MAC: A Unified Framework for Optimization of High-Performance Multipliers and Multiply-Accumulators
by: Zuo, Dongsheng, et al.
Published: (2024)

Commercial Evaluation of Zero-Skipping MAC Design for Bit Sparsity Exploitation in DL Inference
by: Nair, Harideep, et al.
Published: (2024)

A Stochastic Rounding-Enabled Low-Precision Floating-Point MAC for DNN Training
by: Ali, Sami Ben, et al.
Published: (2024)

CHAOS: Controlled Hardware fAult injectOr System for gem5
by: Vinciguerra, Elio, et al.
Published: (2026)

Hardware Acceleration of Kolmogorov-Arnold Network (KAN) for Lightweight Edge Inference
by: Huang, Wei-Hsing, et al.
Published: (2024)

Hardware Acceleration of Kolmogorov-Arnold Network (KAN) in Large-Scale Systems
by: Huang, Wei-Hsing, et al.
Published: (2025)

elasticAI.explorer: Towards a Unified End-to-End Framework for Hardware-Aware Neural Architecture Search
by: Maman, Natalie, et al.
Published: (2026)

Comprehensive Design Space Exploration for Tensorized Neural Network Hardware Accelerators
by: Zhang, Jinsong, et al.
Published: (2025)

Enabling Efficient Hardware Acceleration of Hybrid Vision Transformer (ViT) Networks at the Edge
by: Dumoulin, Joren, et al.
Published: (2025)

Sustainable Hardware Specialization
by: Dangi, Pranav, et al.
Published: (2024)

CiMNet: Towards Joint Optimization for DNN Architecture and Configuration for Compute-In-Memory Hardware
by: Kundu, Souvik, et al.
Published: (2024)

X-HEEP: An Open-Source, Configurable and Extendible RISC-V Microcontroller for the Exploration of Ultra-Low-Power Edge Accelerators
by: Machetti, Simone, et al.
Published: (2024)

A Fully-Configurable Open-Source Software-Defined Digital Quantized Spiking Neural Core Architecture
by: Matinizadeh, Shadi, et al.
Published: (2024)