Saved in:
| Main Authors: | Li, Ang, Wu, Haolin, Wu, Yizhuo, Chen, Qinyu, de Vreede, Leo C. N., Gao, Chang |
|---|---|
| Format: | Preprint |
| Published: |
2024
|
| Subjects: | |
| Online Access: | https://arxiv.org/abs/2410.11766 |
| Tags: |
Add Tag
No Tags, Be the first to tag this record!
|
Similar Items
SparseDPD: A Sparse Neural Network-based Digital Predistortion FPGA Accelerator for RF Power Amplifier Linearization
by: Versluis, Manno, et al.
Published: (2025)
by: Versluis, Manno, et al.
Published: (2025)
MP-DPD: Low-Complexity Mixed-Precision Neural Networks for Energy-Efficient Digital Predistortion of Wideband Power Amplifiers
by: Wu, Yizhuo, et al.
Published: (2024)
by: Wu, Yizhuo, et al.
Published: (2024)
OpenDPD: An Open-Source End-to-End Learning & Benchmarking Framework for Wideband Power Amplifier Modeling and Digital Pre-Distortion
by: Wu, Yizhuo, et al.
Published: (2024)
by: Wu, Yizhuo, et al.
Published: (2024)
DeltaDPD: Exploiting Dynamic Temporal Sparsity in Recurrent Neural Networks for Energy-Efficient Wideband Digital Predistortion
by: Wu, Yizhuo, et al.
Published: (2025)
by: Wu, Yizhuo, et al.
Published: (2025)
A 33.6-136.2 TOPS/W Nonlinear Analog Computing-In-Memory Macro for Multi-bit LSTM Accelerator in 65 nm CMOS
by: Yang, Junyi, et al.
Published: (2025)
by: Yang, Junyi, et al.
Published: (2025)
Clo-HDnn: A 4.66 TFLOPS/W and 3.78 TOPS/W Continual On-Device Learning Accelerator with Energy-efficient Hyperdimensional Computing via Progressive Search
by: Song, Chang Eun, et al.
Published: (2025)
by: Song, Chang Eun, et al.
Published: (2025)
A 16 nm 1.60TOPS/W High Utilization DNN Accelerator with 3D Spatial Data Reuse and Efficient Shared Memory Access
by: Yi, Xiaoling, et al.
Published: (2026)
by: Yi, Xiaoling, et al.
Published: (2026)
TCN-DPD: Parameter-Efficient Temporal Convolutional Networks for Wideband Digital Predistortion
by: Duan, Huanqiang, et al.
Published: (2025)
by: Duan, Huanqiang, et al.
Published: (2025)
JaneEye: A 12-nm 2K-FPS 18.9-$μ$J/Frame Event-based Eye Tracking Accelerator
by: Han, Tao, et al.
Published: (2025)
by: Han, Tao, et al.
Published: (2025)
Siracusa: A 16 nm Heterogenous RISC-V SoC for Extended Reality with At-MRAM Neural Engine
by: Prasad, Arpan Suravi, et al.
Published: (2023)
by: Prasad, Arpan Suravi, et al.
Published: (2023)
CHIMERA: A Flexible and Scalable 3.1 TOPS/W AI-MCU with Transformer Accelerator and 563 Gb/s Shared-L2 Memory Subsystem with QoS Guarantees
by: Leone, Lorenzo, et al.
Published: (2026)
by: Leone, Lorenzo, et al.
Published: (2026)
FSL-HDnn: A 5.7 TOPS/W End-to-end Few-shot Learning Classifier Accelerator with Feature Extraction and Hyperdimensional Computing
by: Yang, Haichao, et al.
Published: (2024)
by: Yang, Haichao, et al.
Published: (2024)
A 71.2-$μ$W Speech Recognition Accelerator with Recurrent Spiking Neural Network
by: Yang, Chih-Chyau, et al.
Published: (2025)
by: Yang, Chih-Chyau, et al.
Published: (2025)
Accelerating Sparse Graph Neural Networks with Tensor Core Optimization
by: Wu, Ka Wai
Published: (2024)
by: Wu, Ka Wai
Published: (2024)
ReLANCE: A Resource-Efficient Low-Latency Cortical Neural Acceleration Engine
by: Kumar, Sonu, et al.
Published: (2025)
by: Kumar, Sonu, et al.
Published: (2025)
Quantized Context Based LIF Neurons for Recurrent Spiking Neural Networks in 45nm
by: Bezugam, Sai Sukruth, et al.
Published: (2024)
by: Bezugam, Sai Sukruth, et al.
Published: (2024)
ACNPU: A 4.75TOPS/W 1080P@30FPS Super Resolution Accelerator with Decoupled Asymmetric Convolution
by: Yang, Tun-Hao, et al.
Published: (2023)
by: Yang, Tun-Hao, et al.
Published: (2023)
Adaptive Robotic Arm Control with a Spiking Recurrent Neural Network on a Digital Accelerator
by: Linares-Barranco, Alejandro, et al.
Published: (2024)
by: Linares-Barranco, Alejandro, et al.
Published: (2024)
IMAGine: An In-Memory Accelerated GEMV Engine Overlay
by: Kabir, MD Arafat, et al.
Published: (2024)
by: Kabir, MD Arafat, et al.
Published: (2024)
Accelerating CRONet on AMD Versal AIE-ML Engines
by: Mhatre, Kaustubh, et al.
Published: (2026)
by: Mhatre, Kaustubh, et al.
Published: (2026)
A Jammer-Resilient 2.87 mm$^2$ 1.28 MS/s 310 mW Multi-Antenna Synchronization ASIC in 65 nm
by: Arquint, Flurin, et al.
Published: (2025)
by: Arquint, Flurin, et al.
Published: (2025)
Leveraging Recurrent Patterns in Graph Accelerators
by: Rahimi, Masoud, et al.
Published: (2025)
by: Rahimi, Masoud, et al.
Published: (2025)
PiC-BNN: A 128-kbit 65 nm Processing-in-CAM-Based End-to-End Binary Neural Network Accelerator
by: Harary, Yuval, et al.
Published: (2026)
by: Harary, Yuval, et al.
Published: (2026)
Efficient Nonlinear Function Approximation in Analog Resistive Crossbars for Recurrent Neural Networks
by: Yang, Junyi, et al.
Published: (2024)
by: Yang, Junyi, et al.
Published: (2024)
A 65-nm Reliable 6T CMOS SRAM Cell with Minimum Size Transistors
by: Torrens, Gabriel, et al.
Published: (2024)
by: Torrens, Gabriel, et al.
Published: (2024)
STI-SNN: A 0.14 GOPS/W/PE Single-Timestep Inference FPGA-based SNN Accelerator with Algorithm and Hardware Co-Design
by: Wang, Kainan, et al.
Published: (2025)
by: Wang, Kainan, et al.
Published: (2025)
Prosperity: Accelerating Spiking Neural Networks via Product Sparsity
by: Wei, Chiyue, et al.
Published: (2025)
by: Wei, Chiyue, et al.
Published: (2025)
An All-digital 8.6-nJ/Frame 65-nm Tsetlin Machine Image Classification Accelerator
by: Tunheim, Svein Anders, et al.
Published: (2025)
by: Tunheim, Svein Anders, et al.
Published: (2025)
HENNC: Hardware Engine for Artificial Neural Network-based Chaotic Oscillators
by: Vaziri, Mobin, et al.
Published: (2024)
by: Vaziri, Mobin, et al.
Published: (2024)
FETTA: Flexible and Efficient Hardware Accelerator for Tensorized Neural Network Training
by: Lu, Jinming, et al.
Published: (2025)
by: Lu, Jinming, et al.
Published: (2025)
TransDot: An Area-efficient Reconfigurable Floating-Point Unit for Trans-Precision Dot-Product Accumulation for FPGA AI Engines
by: Wang, Jiayi, et al.
Published: (2026)
by: Wang, Jiayi, et al.
Published: (2026)
Accelerating Elliptic Curve Point Additions on Versal AI Engine for Multi-scalar Multiplication
by: Ohno, Ayumi, et al.
Published: (2025)
by: Ohno, Ayumi, et al.
Published: (2025)
GAMA: High-Performance GEMM Acceleration on AMD Versal ML-Optimized AI Engines
by: Mhatre, Kaustubh, et al.
Published: (2025)
by: Mhatre, Kaustubh, et al.
Published: (2025)
TYTAN: Taylor-series based Non-Linear Activation Engine for Deep Learning Accelerators
by: Pramanik, Soham, et al.
Published: (2025)
by: Pramanik, Soham, et al.
Published: (2025)
LogicSparse: Enabling Engine-Free Unstructured Sparsity for Quantised Deep-learning Accelerators
by: Li, Changhong, et al.
Published: (2025)
by: Li, Changhong, et al.
Published: (2025)
BF-IMNA: A Bit Fluid In-Memory Neural Architecture for Neural Network Acceleration
by: Rakka, Mariam, et al.
Published: (2024)
by: Rakka, Mariam, et al.
Published: (2024)
FSL-HDnn: A 40 nm Few-shot On-Device Learning Accelerator with Integrated Feature Extraction and Hyperdimensional Computing
by: Xu, Weihong, et al.
Published: (2025)
by: Xu, Weihong, et al.
Published: (2025)
A 0.5V, 6.2$μ$W, 0.059mm$^{2}$ Sinusoidal Current Generator IC with 0.088% THD for Bio-Impedance Sensing
by: Kim, Kwantae, et al.
Published: (2024)
by: Kim, Kwantae, et al.
Published: (2024)
Memory-Guided Unified Hardware Accelerator for Mixed-Precision Scientific Computing
by: Wang, Chuanzhen, et al.
Published: (2026)
by: Wang, Chuanzhen, et al.
Published: (2026)
CIMPool: Scalable Neural Network Acceleration for Compute-In-Memory using Weight Pools
by: Li, Shurui, et al.
Published: (2025)
by: Li, Shurui, et al.
Published: (2025)
Similar Items
-
SparseDPD: A Sparse Neural Network-based Digital Predistortion FPGA Accelerator for RF Power Amplifier Linearization
by: Versluis, Manno, et al.
Published: (2025) -
MP-DPD: Low-Complexity Mixed-Precision Neural Networks for Energy-Efficient Digital Predistortion of Wideband Power Amplifiers
by: Wu, Yizhuo, et al.
Published: (2024) -
OpenDPD: An Open-Source End-to-End Learning & Benchmarking Framework for Wideband Power Amplifier Modeling and Digital Pre-Distortion
by: Wu, Yizhuo, et al.
Published: (2024) -
DeltaDPD: Exploiting Dynamic Temporal Sparsity in Recurrent Neural Networks for Energy-Efficient Wideband Digital Predistortion
by: Wu, Yizhuo, et al.
Published: (2025) -
A 33.6-136.2 TOPS/W Nonlinear Analog Computing-In-Memory Macro for Multi-bit LSTM Accelerator in 65 nm CMOS
by: Yang, Junyi, et al.
Published: (2025)