Low-Power Encoding for PAM-3 DRAM Bus
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arXiv
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| Main Authors: | , , |
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| Format: | Preprint |
| Published: |
2024
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| _version_ | 1866910653991616512 |
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| author | Nam, Jonghyeon Han, Jaeduk Kim, Hokeun |
| author_facet | Nam, Jonghyeon Han, Jaeduk Kim, Hokeun |
| contents | The 3-level pulse amplitude modulation (PAM-3) signaling is expected to be widely used in memory interfaces for its greater voltage margins compared to PAM-4. To maximize the benefit of PAM-3, we propose three low-power data encoding algorithms: PAM3-DBI, PAM3-MF, and PAM3-SORT. With the DRAM memory traces from the gem5 computer architecture simulator running benchmarks, we evaluate the energy efficiency of our three PAM-3 encoding techniques. The experimental results show the proposed algorithms can reduce termination power for high-speed memory links significantly by 41% to 90% for benchmark programs. |
| format | Preprint |
| id |
arxiv_https___arxiv_org_abs_2410_12990 |
| institution | arXiv |
| publishDate | 2024 |
| record_format | arxiv |
| spellingShingle | Low-Power Encoding for PAM-3 DRAM Bus Nam, Jonghyeon Han, Jaeduk Kim, Hokeun Systems and Control Hardware Architecture The 3-level pulse amplitude modulation (PAM-3) signaling is expected to be widely used in memory interfaces for its greater voltage margins compared to PAM-4. To maximize the benefit of PAM-3, we propose three low-power data encoding algorithms: PAM3-DBI, PAM3-MF, and PAM3-SORT. With the DRAM memory traces from the gem5 computer architecture simulator running benchmarks, we evaluate the energy efficiency of our three PAM-3 encoding techniques. The experimental results show the proposed algorithms can reduce termination power for high-speed memory links significantly by 41% to 90% for benchmark programs. |
| title | Low-Power Encoding for PAM-3 DRAM Bus |
| topic | Systems and Control Hardware Architecture |
| url | https://arxiv.org/abs/2410.12990 |