Cover Image

RapidStream IR: Infrastructure for FPGA High-Level Physical Synthesis

Fuente: arXiv

Saved in:

Bibliographic Details
Main Authors:	Lau, Jason, Xiao, Yuanlong, Xie, Yutong, Chi, Yuze, Song, Linghao, Xiang, Shaojie, Lo, Michael, Zhang, Zhiru, Cong, Jason, Guo, Licheng
Format:	Preprint
Published:	2024
Subjects:	Hardware Architecture Distributed, Parallel, and Cluster Computing 68M99
Online Access:	Acceder al recurso
Tags:	Add Tag No Tags, Be the first to tag this record!

Similar Items

TAPA-CS: Enabling Scalable Accelerator Design on Distributed HBM-FPGAs
by: Prakriya, Neha, et al.
Published: (2023)

TAPA: A Scalable Task-Parallel Dataflow Programming Framework for Modern FPGAs with Co-Optimization of HLS and Physical Design
by: Guo, Licheng, et al.
Published: (2022)

RapidOMS: FPGA-based Open Modification Spectral Library Searching with HD Computing
by: Pinge, Sumukh, et al.
Published: (2024)

DP-HLS: A High-Level Synthesis Framework for Accelerating Dynamic Programming Algorithms in Bioinformatics
by: Cao, Yingqi, et al.
Published: (2024)

MLDSE: Scaling Design Space Exploration Infrastructure for Multi-Level Hardware
by: Qu, Huanyu, et al.
Published: (2025)

ML-QLS: Multilevel Quantum Layout Synthesis
by: Lin, Wan-Hsuan, et al.
Published: (2024)

Accelerating Recommender Model ETL with a Streaming FPGA-GPU Dataflow
by: Zhu, Yu, et al.
Published: (2025)

FPGA Innovation Research in the Netherlands: Present Landscape and Future Outlook
by: Alachiotis, Nikolaos, et al.
Published: (2025)

EPOCH: Enabling Preemption Operation for Context Saving in Heterogeneous FPGA Systems
by: Malik, Arsalan Ali, et al.
Published: (2025)

Enabling Time-Aware Priority Traffic Management over Distributed FPGA Nodes
by: Scionti, Alberto, et al.
Published: (2025)

FLEX: Leveraging FPGA-CPU Synergy for Mixed-Cell-Height Legalization Acceleration
by: Liu, Xingyu, et al.
Published: (2025)

Context-aware Simopt-Power: Using structural data with simulation metadata to optimise FPGA designs
by: Wadhwa, Eashan, et al.
Published: (2026)

MANOJAVAM: A Scalable, Unified FPGA Accelerator for Matrix Multiplication and Singular Value Decomposition in Principal Component Analysis
by: Ramasubramanian, Srivaths, et al.
Published: (2026)

xPUE: Extending Power Usage Effectiveness Metrics for Cloud Infrastructures
by: Fieni, Guillaume, et al.
Published: (2025)

Simopt -- Simulation pass for Speculative Optimisation of FPGA-CAD flow
by: Wadhwa, Eashan, et al.
Published: (2024)

Evaluating Rapid Makespan Predictions for Heterogeneous Systems with Programmable Logic
by: Wilhelm, Martin, et al.
Published: (2025)

Cloud-Native Operation of Roadside Infrastructure Enabling Demand-Driven Collective Perception via V2X
by: Zanger, Lukas, et al.
Published: (2026)

PUDTune: Multi-Level Charging for High-Precision Calibration in Processing-Using-DRAM
by: Kubo, Tatsuya, et al.
Published: (2025)

Can Asymmetric Tile Buffering Be Beneficial?
by: Wang, Chengyue, et al.
Published: (2025)

Accelerating Transposed Convolutions on FPGA-based Edge Devices
by: Haris, Jude, et al.
Published: (2025)

NeuroRing: Scaling Spiking Neural Networks via Multi-FPGA Bidirectional Ring Topologies and Stream-Dataflow Architectures
by: Hafiz, Muhammad Ihsan Al, et al.
Published: (2026)

Chopper: A Multi-Level GPU Characterization Tool & Derived Insights Into LLM Training Inefficiency
by: Kurzynski, Marco, et al.
Published: (2025)

The DMA Streaming Framework: Kernel-Level Buffer Orchestration for High-Performance AI Data Paths
by: Graziano, Marco
Published: (2026)

The Feasibility of Implementing Large-Scale Transformers on Multi-FPGA Platforms
by: Gao, Yu, et al.
Published: (2024)

Exploring Parallelism in FPGA-Based Accelerators for Machine Learning Applications
by: Centeno, Sed, et al.
Published: (2025)

Security Risks Due to Data Persistence in Cloud FPGA Platforms
by: Zhang, Zhehang, et al.
Published: (2024)

Design in Tiles: Automating GEMM Deployment on Tile-Based Many-PE Accelerators
by: Shen, Aofeng, et al.
Published: (2025)

A Survey on Graph Neural Network Acceleration: Algorithms, Systems, and Customized Hardware
by: Zhang, Shichang, et al.
Published: (2023)

Efficient Edge AI: Deploying Convolutional Neural Networks on FPGA with the Gemmini Accelerator
by: Peccia, Federico Nicolas, et al.
Published: (2024)

PIUMA: Programmable Integrated Unified Memory Architecture
by: Aananthakrishnan, Sriram, et al.
Published: (2020)

TeraPool: A Physical Design Aware, 1024 RISC-V Cores Shared-L1-Memory Scaled-up Cluster Design with High Bandwidth Main Memory Link
by: Zhang, Yichao, et al.
Published: (2026)

Atomique: A Quantum Compiler for Reconfigurable Neutral Atom Arrays
by: Wang, Hanrui, et al.
Published: (2023)

Observation, Not Prediction: Conversation-Level Disaggregated Scheduling for Agentic Serving
by: Ding, Jianru, et al.
Published: (2026)

Dissecting the NVIDIA Hopper Architecture through Microbenchmarking and Multiple Level Analysis
by: Luo, Weile, et al.
Published: (2025)

A Reliable, Time-Predictable Heterogeneous SoC for AI-Enhanced Mixed-Criticality Edge Applications
by: Garofalo, Angelo, et al.
Published: (2025)

Efficient Batch Search Algorithm for B+ Tree Index Structures with Level-Wise Traversal on FPGAs
by: Tzschoppe, Max, et al.
Published: (2026)

SnapStream: Efficient Long Sequence Decoding on Dataflow Accelerators
by: Li, Jonathan, et al.
Published: (2025)

Intent-Driven Storage Systems: From Low-Level Tuning to High-Level Understanding
by: Bergman, Shai, et al.
Published: (2025)

TT-Edge: A Hardware-Software Co-Design for Energy-Efficient Tensor-Train Decomposition on Edge AI
by: Kwak, Hyunseok, et al.
Published: (2025)

The DEEP-ER project: I/O and resiliency extensions for the Cluster-Booster architecture
by: Kreuzer, Anke, et al.
Published: (2019)